mirror of
https://github.com/fail0verflow/switch-coreboot.git
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7c14a50c1c
I introduced earlier. It adds a placeholder in the fintek SuperIO so the array indexing works. It moves the enable to make the struct more compatible with v2. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1066 f3766cd6-281f-0410-b1cd-43a5c92072e9
106 lines
3.5 KiB
C
106 lines
3.5 KiB
C
/*
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* Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
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* Copyright (C) 2007 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef DEVICE_PNP_H
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#define DEVICE_PNP_H
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#include <types.h>
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#include <device/device.h>
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/* Very low-level PNP functions, mostly intended for stage 0 or 1 */
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void rawpnp_enter_ext_func_mode(u16 port);
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void rawpnp_exit_ext_func_mode(u16 port);
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void rawpnp_write_config(u16 port, u8 reg, u8 value);
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u8 rawpnp_read_config(u16 port, u8 reg);
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void rawpnp_set_logical_device(u16 port, u8 ldn);
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void rawpnp_set_enable(u16 port, int enable);
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void rawpnp_set_iobase(u16 port, u8 index, u16 iobase);
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/* Primitive pnp resource manipulation */
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void pnp_write_config(struct device * dev, u8 reg, u8 value);
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u8 pnp_read_config(struct device * dev, u8 reg);
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void pnp_set_logical_device(struct device * dev);
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void pnp_set_enable(struct device * dev, int enable);
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int pnp_read_enable(struct device * dev);
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void pnp_set_iobase(struct device * dev, unsigned index, unsigned iobase);
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void pnp_set_irq(struct device * dev, unsigned index, unsigned irq);
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void pnp_set_drq(struct device * dev, unsigned index, unsigned drq);
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/* PNP device operations */
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void pnp_read_resources(struct device * dev);
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void pnp_set_resources(struct device * dev);
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void pnp_enable_resources(struct device * dev);
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void pnp_enable(struct device * dev);
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extern struct device_operations pnp_ops;
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/* PNP helper operations */
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struct io_info {
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unsigned mask, set, val;
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};
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struct pnp_info {
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struct device_operations *ops;
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unsigned function;
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unsigned flags;
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#define PNP_IO0 0x01
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#define PNP_IO1 0x02
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#define PNP_IO2 0x04
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#define PNP_IO3 0x08
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#define PNP_IRQ0 0x10
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#define PNP_IRQ1 0x20
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#define PNP_DRQ0 0x40
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#define PNP_DRQ1 0x80
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struct io_info io0, io1, io2, io3;
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unsigned irq0, irq1, drq0, drq1;
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unsigned enable;
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};
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struct resource *pnp_get_resource(struct device * dev, unsigned index);
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void pnp_enable_devices(struct device *dev, struct device_operations *ops,
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unsigned functions, struct pnp_info *info);
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#define PNP_IDX_IO0 0x60
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#define PNP_IDX_IO1 0x62
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#define PNP_IDX_IO2 0x64
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#define PNP_IDX_IO3 0x66
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#define PNP_IDX_IRQ0 0x70
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#define PNP_IDX_IRQ1 0x72
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#define PNP_IDX_DRQ0 0x74
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#define PNP_IDX_DRQ1 0x75
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/* PNP functions used to enter/exit PNP config mode */
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void pnp_enter_ite_it8661f(struct device *dev);
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void pnp_enter_ite_it8671f(struct device *dev);
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void pnp_enter_ite(struct device *dev);
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void pnp_enter_ite_it8761e(struct device *dev);
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void pnp_enter_ite_it8228e(struct device *dev);
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void pnp_enter_8787(struct device *dev);
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void pnp_enter_ali(struct device *dev);
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void pnp_enter_smsc(struct device *dev);
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void pnp_enter_88(struct device *dev);
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void pnp_enter_89(struct device *dev);
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void pnp_enter_8686(struct device *dev);
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void pnp_exit_aa(struct device *dev);
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void pnp_exit_ite(struct device *dev);
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void pnp_exit_ali(struct device *dev);
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#endif /* DEVICE_PNP_H */
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