mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
d96aab9e06
- VIA 686 cleanups from the A7M code (it now works in a different pci slot). - Update of assembly printing routines to use the debug levels: TTYS0_TX_CHAR now becomes CONSOLE_<LEVEL>_TX_CHAR. It's more verbose but now the controls are the same as with the C code. - Break off of loglevel.h from printk.h. loglevel.h is safe for both the assembly routines and the C code to include. - Next round of commits for the supermicro p4dc6 - SMP setup updates (Rons board is broken) I now allow the other SMP processors to report their existence. I really need to add a minimum time to run but that hasn't happened yet. - SMP per motherboard table of apicids, as the assumption that they would always be 0 & 1 with only two cpus fails. - RDRAM setup updates. The code isn't done but it now works on more than one board at a time. - More cacheram work. Minor bug fixes and some macros to use it from C. - Entry point changes so we no longer have to jump over our gdt. - Added/Audited the cpufixup for the i786 - IDE intialization for the 82801 ich2 chip.
345 lines
9.5 KiB
Text
345 lines
9.5 KiB
Text
The goal of this document is to define the configuration language for
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LinuxBIOS. We have looked at both the Linux CML and CML2; as well as
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BSD config. For various reasons, none of these work for what we
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need. What we need is something that lets us maintain lots of
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platforms out of one source tree (so the Linux way of doing things is
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out); at the same time, most of the BSD config language is too
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specific to kernels, is rather complex, and now supports editing of
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kernel binaries, which we don't need. Our needs are pretty simple, so
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we're going to try to cut our own. Since we hope to support
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non-Pentium architectures at some point, we're going to try to base
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this on an interpretive language. Since the person who has volunteered
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to do this knows Python well, we're going to use Python.
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Basics
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It looks like we're going to write the tool in Python. Rather than
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shoot for a full BNF (seems like overkill just now) we're going to try
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a simple textual description, since a BNF won't get us anywhere with
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Python anyway. (no YACC available in Python).
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A config file consists of commands and comments. Comments are
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Python-style. Commands consist of a keyword, an argument, and
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optional modifiers. Keywords and arguments are variable names as
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defined in Python. Values are quote-strings or numbers; numbers follow
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the C rules (i.e. 0x for hex, etc.). Commands are lower case. Commands
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and comments may be interspersed arbitrarily; for example, even though
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the target command must be first, it may be preceded by comments.
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Environment variables
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TOP
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TOP is the top of the bios source tree. All file substitutions are
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done relative to $(TOP). If TOP is not set, it is assumed to be
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"../". Note that relative pathnames should always be used.
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Commands
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target <target-name>
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target must be the first command in the file. This command may only be
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used once. target names the target directory for building this
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instance of the BIOS. The target directory will be in
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$(TOP)/<target-name>.
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mainboard <mainboard name>
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The second command in the file is the mainboard command. This command
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may only be used once. The mainboard command names a mainboard source
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directory to use. If the file $(TOP)/src/<mainboard name>/Config
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exists, that file is opened and the commands in that file are executed.
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cpu <cpu name>
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This command may only be used once for a given CPU name. If the file
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$(TOP)/src/cpu/<cpu name>/Config exists, it is opened and commands in that
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file are executed.
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northbridge <vendor> <northbridge name>
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This command may only be used once. If the file
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$(TOP)/src/northbridge/vendor/<northbridge name>/Config exists, it is
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opened and commands in that file are executed.
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southbridge <vendor> <southbridge name>
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This command may only be used once. If the file
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$(TOP)/src/southbridge/vendor/<southbridge name>/Config exists, it is
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opened and commands in that file are executed.
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pcibridge <vendor> <bridge name>
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This command may be used as many times as needed. If the file
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$(TOP)/src/pcibridge/vendor/<pcibridge name>/Config exists, it is
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opened and commands in that file are executed.
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superio <vendor> <superio name>
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This command may be used as many times as needed. If the file
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$(TOP)/src/superio/vendor/<superio name>/Config exists, it is
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opened and commands in that file are executed.
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object <path-to-source>
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<path-to-source> is a pathname to a .c or .S file rooted at
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$(TOP)/<path-to-source>. This command adds a rule to the Makefile for
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the target such that:
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1) Basename of <path-to-source>.o depends on $(TOP)/<path-to-source>
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2) romimage has a dependency on the .o
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3) includepath for compiling the .o includes the directory containing the
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source
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option <option-name> [<optional value>]
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This command affects the CFLAGS for the generated Makefile. If there is
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no optional value, then the option should appear in CFLAGS as:
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CFLAGS += -D<option-name>
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If there is a value, then the option should appear as:
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CFLAGS += -D<option-name>=<optional value>
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Sample Makefile
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Here from the existing LinuxBIOS is a sample Makefile.
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TOP=../..
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INCLUDES=-I $(TOP)/include -I. -I $(TOP)/linuxbios/include
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CFLAGS=$(INCLUDES) -O2 $(CPUFLAGS) -Ilinux/include -Wall
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# you need to include some linux files. You should use the linux soft link
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# in this directory, so you ensure you get the right includes!
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LINUXINCLUDE=-Ilinux/include
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OBJECTS=crt0.o main.o intel_main.o intel_mtrr.o intel_subr.o fill_inbuf.o params.o
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#OBJECTS += pci.o
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OBJECTS += printk.o vsprintf.o
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OBJECTS += newpci.o linuxpci.o
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OBJECTS += intel_cpuid.o intel_irq_tables.o
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OBJECTS += serial_subr.o
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OBJECTS += intel_mpspec.o
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OBJECTS += intel_microcode.o
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LINK = ld -T ldscript.ld -o $@ $(OBJECTS)
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CC=cc $(CFLAGS)
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CCASM=cc -I$(TOP)/chip/intel $(CFLAGS)
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# this is in for broken GAS
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# if you have problems with the crt0.S, something about garbage after
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# the data32, try setting this:
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# setenv BROKEN_GAS -DBROKEN_GAS
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# Not a problem for 2.9.5 and later.
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CFLAGS += $(BROKEN_GAS)
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all: romimage
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floppy: all
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mcopy -o romimage a:
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# here's the problem: we shouldn't assume we come up with more than
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# 64K of FLASH up. SO we need a working linuxbios at the tail, and it will
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# enable all flash and then gunzip the linuxbios. As a result,
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# we need the vmlinux.bin.gz padded out and then cat the linuxbios.rom
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# at then end. We always copy it to /tmp so that a waiting root shell
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# can put it on the floppy (see ROOTDOIT)
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romimage: linuxbios.rom vmlinux.bin.gz.block
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cat vmlinux.bin.gz.block linuxbios.rom > romimage
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cp romimage /tmp
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linuxbios.rom: linuxbios.strip mkrom
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./mkrom -s 64 -f -o linuxbios.rom linuxbios.strip
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linuxbios.strip: linuxbios
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objcopy -O binary -R .note -R .comment -S linuxbios linuxbios.strip
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linuxbios: $(OBJECTS) vmlinux.bin.gz
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@rm -f biosobject
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$(LINK)
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nm -n linuxbios > linuxbios.map
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crt0.s: crt0.S
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$(CCASM) -E crt0.S > crt0.s
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crt0.o : crt0.s
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$(CCASM) -c crt0.s
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mkrom: $(TOP)/mkrom/mkrom.c
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cc -o mkrom $<
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main.o: ../inflate/main.c
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cc $(CFLAGS) -c ../inflate/main.c
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fill_inbuf.o: ../inflate/fill_inbuf.c
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cc $(CFLAGS) -c ../inflate/fill_inbuf.c
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params.o: ../lib/params.c
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cc $(CFLAGS) $(LINUXINCLUDE) -c ../lib/params.c
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intel_main.o: ../../chip/intel/intel_main.c
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cc $(CFLAGS) -c $<
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pci.o: ../../chip/intel/pci.c
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cc $(CFLAGS) -c $<
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intel_irq_tables.o: ../../chip/intel/intel_irq_tables.c
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cc $(CFLAGS) -o $@ -c $<
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intel_mtrr.o: ../../chip/intel/intel_mtrr.c
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cc $(CFLAGS) -c $<
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intel_subr.o: ../../chip/intel/intel_subr.c
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cc $(CFLAGS) -c $<
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intel_cpuid.o: $(TOP)/chip/intel/intel_cpuid.c
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cc $(CFLAGS) -c $<
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intel_mpspec.o: $(TOP)/chip/intel/intel_mpspec.c
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$(CC) $(CFLAGS) -c $<
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intel_microcode.o: $(TOP)/chip/intel/intel_microcode.c
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$(CC) $(CFLAGS) -c $<
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serial_subr.o: $(TOP)/chip/intel/serial_subr.c
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cc $(CFLAGS) -c $<
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printk.o: $(TOP)/lib/printk.c
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cc $(CFLAGS) -c $<
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vsprintf.o: $(TOP)/lib/vsprintf.c
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cc $(CFLAGS) -c $<
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newpci.o: $(TOP)/lib/newpci.c
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cc $(CFLAGS) -c $<
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linuxpci.o: $(TOP)/lib/linuxpci.c
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cc $(CFLAGS) -c $<
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vmlinux.bin.gz.block: vmlinux.bin.gz
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dd conv=sync bs=448k if=vmlinux.bin.gz of=vmlinux.bin.gz.block
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vmlinux.bin.gz: vmlinux.bin
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gzip -f -3 vmlinux.bin
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vmlinux.bin: linux/vmlinux
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objcopy -O binary -R .note -R .comment -S $< vmlinux.bin
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alltags:
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gctags ../inflate/*.c ../../lib/*.c ../../chip/intel/*.c
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etags ../inflate/*.c ../../lib/*.c ../../chip/intel/*.c
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clean::
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rm -f linuxbios.* vmlinux.* *.o mkrom xa? *~ linuxbios romimage crt0.s
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rm -f a.out *.s *.l
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rm -f TAGS tags
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Sample crt0.S
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Here is a sample crt0.S from the existing LinuxBIOS.
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/*
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* $ $
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*
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*/
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#include <rom/asm.h>
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#include <rom/intel.h>
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#include "intel_conf.h"
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#include <sis630.h>
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/*
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* This is the entry code (the mkrom(8) utility makes a jumpvector
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* to this adddess.
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*
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* When we get here we are in x86 real mode.
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*
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* %cs = 0xf000 %ip = 0x0000
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* %ds = 0x0000 %es = 0x0000
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* %dx = 0x0yxx (y = 3 for i386, 5 for pentium, 6 for P6,
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* where x is undefined)
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* %fl = 0x0002
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*/
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.text
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.code16
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#include "intel_start32.S"
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/* turn on serial */
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#include "VIA_VT82C686A.S"
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#include "serial.S"
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#include <arch/i386/lib/console.inc>
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CONSOLE_DEBUG_TX_STRING($ttyS0_test)
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/* initialize the RAM */
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/* different for each motherboard */
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#include "intel_pm133ram.S"
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#ifdef RAMTEST
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#include "ramtest.S"
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#include "./intel_mtrr.S"
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mov $0x00000000, %eax
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mov $0x0009ffff, %ebx
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mov $16, %ecx
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CALLSP(ramtest)
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#endif
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/*
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* Copy data into RAM and clear the BSS. Since these segments
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* isn't really that big we just copy/clear using bytes, not
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* double words.
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*/
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intel_chip_post_macro(0x11) /* post 11 */
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CONSOLE_DEBUG_TX_STRING($str_after_ram)
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cld /* clear direction flag */
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leal EXT(_ldata), %esi
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leal EXT(_data), %edi
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movl $EXT(_eldata), %ecx
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subl %esi, %ecx
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jz .Lnodata /* should not happen */
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rep
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movsb
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.Lnodata:
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intel_chip_post_macro(0x12) /* post 12 */
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CONSOLE_DEBUG_TX_STRING($str_after_copy)
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/** clear stack */
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xorl %edi, %edi
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movl $_PDATABASE, %ecx
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xorl %eax, %eax
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rep
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stosb
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/** clear bss */
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leal EXT(_bss), %edi
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movl $EXT(_ebss), %ecx
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subl %edi, %ecx
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jz .Lnobss
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xorl %eax, %eax
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rep
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stosb
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.Lnobss:
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/*
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* Now we are finished. Memory is up, data is copied and
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* bss is cleared. Now we call the ``main<69><6E> routine and
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* let it do the rest.
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*/
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intel_chip_post_macro(0xfe) /* post fe */
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CONSOLE_DEBUG_TX_STRING($str_pre_main)
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/* set new stack */
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movl $_PDATABASE, %esp
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/* memory is up. Let's do the rest in C -- much easier. */
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call EXT(intel_main)
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/*NOTREACHED*/
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.Lhlt: hlt
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jmp .Lhlt
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ttyS0_test: .string "\r\n\r\nHello world!!\r\n"
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str_after_ram: .string "Ram Initialize?\r\n"
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str_after_copy: .string "after copy?\r\n"
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str_pre_main: .string "before main\r\n"
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newline: .string "\r\n"
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