- Coding style and whitespace fixes.
- Remove obsolete comments, fix incorrect ones.
- Use the full/canonical name of mainboards/vendors everywhere.
- Update the list of USB Debug capable chipsets from
http://www.coreboot.org/EHCI_Debug_Port.
- s/LB/CB/ for the CONSOLE_PREFIX kconfig option.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@879 f3766cd6-281f-0410-b1cd-43a5c92072e9
mainboard that we learned with the serengeti that we needed. New
function in pnp that is for reading. new prototype in pnp.h. New
constants for ite8716f.
This board does not build yet; we are exercising code in k8 north that
the serengeti did not enable. More tomorrow.
Now that we have two boards under way we can hopefully see our way to
getting more put in. The 690 is the obvious next choice.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@876 f3766cd6-281f-0410-b1cd-43a5c92072e9
multiple links. The way this was done in v2 was a big confusing; this way is
less so.
The changes are easy. Getting them right has been hard :-)
First, for a k8 north that has three links, you can name each one as follows:
pci0@18,0
pci1@18,0
pci2@18,0
We have to have the same pcidevfn on these because that is how the k8 works.
But the unit numbers (pci0, pci1, etc.) distinguish them.
The dts will properly generate a "v3 device code"
compatible static tree that puts the links in the right place in the
data structure.
The changes to dts are trivial.
As before, dts nodes with children are understood to be a bridge.
But what if there is a dts entry like this:
pci1@18,0 {/config/("northbridge/amd/k8/pci");};
This entry has no children in the dts.
How does dt compiler know it is a bridge? It can not know unless
we add information to the dts for that northbridge part.
To ensure that all bridge devices are detected, we support the following:
if a dts node for a device has a bridge property, e.g.:
{
device_operations = "k8_ops";
bridge;
};
The dt compiler will treat it as a bridge whether it has children or not.
Why would a device not have children? Because it might be attached to a
pci or other socket, and we don't know at build time if the socket is empty,
or what might be in the socket.
This code has been tested on dbe62 and k8 simnow, and works on each.
It is minimal in size and it does what we need. I hope it resolves our
discussion for now. We might want to improve or change the device code
later but, at this point, forward motion is important -- I'm on a deadline for
a very important demo Oct. 22!
Also included in this patch are new debug prints in k8 north.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@865 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@853 f3766cd6-281f-0410-b1cd-43a5c92072e9
Message level is BIOS_SPEW for everything except error conditions.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@845 f3766cd6-281f-0410-b1cd-43a5c92072e9
This means that basic resource maps are working, initial hypertransport
setup is working, the amd8111 ISA device is working, config space is
working for all the parts, we can grow the FLASH part address space to
more than 64k, and in general we're having a good time.
Here is the output:
coreboot-3.0.824 Tue Aug 26 22:18:21 PDT 2008 starting...
(console_loglevel=8)
Choosing fallback boot.
LAR: Attempting to open 'fallback/initram/segment0'.
LAR: Start 0xfff80000 len 0x80000
LAR: normal/option_table@0xfff80000, size 1776
LAR: normal/initram/segment0@0xfff80740, size 24404
LAR: normal/stage2/segment0@0xfff866f0, size 1
LAR: normal/stage2/segment1@0xfff86750, size 18542
LAR: normal/stage2/segment2@0xfff8b010, size 559
LAR: normal/payload/segment0@0xfff8b290, size 18142
LAR: bootblock@0xffff7fc0, size 32768
LAR: File not found!
LAR: Run file fallback/initram/segment0 failed: No such file.
Fallback failed. Try normal boot
LAR: Attempting to open 'normal/initram/segment0'.
LAR: Start 0xfff80000 len 0x80000
LAR: normal/option_table@0xfff80000, size 1776
LAR: normal/initram/segment0@0xfff80740, size 24404
LAR: CHECK normal/initram/segment0 @ 0xfff80740
start 0xfff80790 len 24404 reallen 24404 compression 0 entry 0x00000004
loadaddress 0x00000000
Entry point is 0xfff80794
Hi there from stage1
stage1 returns
run_file returns with 0
Goal for tomorrow is to get initram done.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@826 f3766cd6-281f-0410-b1cd-43a5c92072e9
Builds both K8 and Geode bioses with no trouble.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnch <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@811 f3766cd6-281f-0410-b1cd-43a5c92072e9
next step is to fix up this:
LAR build/coreboot.rom
Bootblock coreboot.bootblock does not appear to be a bootblock.
Error adding the bootblock to the LAR.
make: *** [/home/rminnich/src/bios/coreboot-v3/build/coreboot.rom] Error
1
make: exit 2
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@809 f3766cd6-281f-0410-b1cd-43a5c92072e9
image, and fails:
LAR build/coreboot.rom
Bootblock coreboot.bootblock does not appear to be a bootblock.
Error adding the bootblock to the LAR.
make: *** [/home/rminnich/src/bios/coreboot-v3/build/coreboot.rom] Error
1
Next step is to get rid of all warnings that are not #warning.
Then it is on to simnow.
Anyone who wants to work on the warnings is most welcome to.
DBE62 still builds with no problems.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@808 f3766cd6-281f-0410-b1cd-43a5c92072e9
Thanks to Ron for explaining this.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@801 f3766cd6-281f-0410-b1cd-43a5c92072e9
It's all REV_F now and we're wasting time pretending otherwise. This
change simplifies the code and will continue to simplify the code.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@788 f3766cd6-281f-0410-b1cd-43a5c92072e9
arguably fixes some strange behaviour and prepares the code for
per-device subsystem ID setting.
It's the first step to achieve the per-device subsystem goal.
Boot tested on qemu.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@761 f3766cd6-281f-0410-b1cd-43a5c92072e9
confusion when analyzing the logs. Improve readability.
This code may be obsolete, but that's not entriely sure yet.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@759 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: : Ronald G. Minnich <rminnich@gmail.com>
smbus_ops patched
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@758 f3766cd6-281f-0410-b1cd-43a5c92072e9
readability. Move to anonymous unions.
Build tested on all targets. Boot tested on qemu.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Ron tested this and it boots to Linux.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@730 f3766cd6-281f-0410-b1cd-43a5c92072e9
(1)we now compile in all printks, which is good: we can print any message provided we can change
the console log level at any time.
(2) The console log level is compiled in and unchangeable, which is bad, as it defeats the purpose of (1).
Add a BIOS_ALWAYS log level. Make console log level a variable. Make functions that set it and get it
visible everywhere. Always print out the version message; this is really *not* noise!
PCI: Simplify pci functions so that they can be used in stage1 or anywhere for that matter. Add
a find function which is needed for many stage1 functions. Note that we copy but also clean up
the libpayload stuff just a bit.
Get rid of config space type 2. If there was ever a platform that used it, I don't know what it was,
and the presence is a needless distraction.
tested and working on DBE62 (which means the console and the pci functions work :-).
There is a remaining problem with dumplxmsrs which nobody understands. It prints out garbage if we use the
%s for the msr names.
Formatting is an issue; if somebody wants to fix formatting they can assume I will ack it. Sorry,
my emacs has gone just nuts.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@729 f3766cd6-281f-0410-b1cd-43a5c92072e9
This creates a clearer distinction between source files in the source
tree we want to have compiled and indirectly created object/source files
in the object tree.
It also will make enable us to move to whole-program
optimization/compilation which should yield substantial size savings.
Then again, we may be able to do that without the makefile conversion as
well.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@714 f3766cd6-281f-0410-b1cd-43a5c92072e9
Compile tested including boundary cases.
Runtime tested on dbe62 by Ron. Works fine.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@693 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Aaron Lwe <aaron.lwe@gmail.com>
Acked-by: Joseph Smith <joe@settoplinux.org>
Tested on v3 and
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
This patch also (accidently) includes
a simple fix for the null pointer reference problem. I had forgotten that
the fix was in there, but I will include it here and hope no one is too upset about
its inclusion.
git-svn-id: svn://coreboot.org/repository/coreboot-v3@669 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@657 f3766cd6-281f-0410-b1cd-43a5c92072e9
changed during run time. (trivial patch)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@651 f3766cd6-281f-0410-b1cd-43a5c92072e9
Add a nasty warning if one of the cases triggers because that should
not happen. We should fix the cases where the warning triggers.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@631 f3766cd6-281f-0410-b1cd-43a5c92072e9
before they can be #included. That is completely counter-intuitive. Add
necessary #includes to the header files themselves.
Fix a few cases where nonexisting files were #included.
Compile tested on Qemu and Alix1C.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@611 f3766cd6-281f-0410-b1cd-43a5c92072e9
code boots and works on qemu and
alix1c. It represents a huge change and a huge improvement. There are a
few fixes left to do, which
will come once this is in.
This change started out easy: get the device IDs OUT of the the dts, and
into one place. We
decided the device IDs should be in the constructors ONLY. To make a
long story short, that just did
not work out, and it revealed a flaw in the design. The result?
- no more ids in the various dts files.
- the constructor struct is gone -- one less struct, nobody liked the
name anyway
- the device_operations struct now includes the device id.
- constructor property no longer used; use device_operations instead.
- lpc replaced with ioport
All the changes below stem from this "simple" change.
I am finding this new structure much easier to work with. I hope we're
done
on this for real, however!
TODO:
1. Change limitation in dtc that makes it hard to use hex in pci@
notation.
Now for the bad news. Sometime today, interrupts or io or something
stopped working between r596 and r602 -- but I did no commits at
that point. So something has gone wrong, but I don't think it's this
stuff.
I did try a build of HEAD, and it fails really, really badly. Much
more badly than this fails, so I think this commit is only going
to improve things. It does work fine on qemu, fails on alix1c,
so I suspect one of today's "clean up commits" broke something.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@603 f3766cd6-281f-0410-b1cd-43a5c92072e9
CONFIG_* == 1. If those variables are set, they will always be 1.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@599 f3766cd6-281f-0410-b1cd-43a5c92072e9
committed, the #if 1 never served any purpose.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@598 f3766cd6-281f-0410-b1cd-43a5c92072e9
The code was blindly copied from v2 in v3:r69. Was never enabled in v2
(committed as dead code by Eric Biederman in v2:r1664 with log message
"Updates for 64bit resource support, handling missing devices and cpus
in the config file").
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@597 f3766cd6-281f-0410-b1cd-43a5c92072e9
those we had in v2 and before r385.
This causes pm_chipset_init() to be called on Geode LX.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Builds and run to filo.
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@595 f3766cd6-281f-0410-b1cd-43a5c92072e9
in dts. This gets rid of the ugly pcipath etc. properties.
So, instead of
somedevice {pcipath="1,0";};
We say pci@1,0{ etc. etc. };
As per my agreement I agree to document this in the design doc.
The alix1c compiles but is untested, and will probably need some work.
I will do these additional tasks on friday.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
M include/device/path.h
Add LPC path type, replacing SUPERIO path type, since SUPERIO is only
one type of LPC. Clean up tabbing in parts of the file (cosmetic).
M mainboard/emulation/qemu-x86/dts
Modify this dts for the new path naming scheme.
M device/pci_device.c
Change what used to be a BIOS_ERR (but is no longer) to a BIOS_NOTICE.
The change is that the device tree includes more than just PCI devices,
so finding a non-PCI device is no longer fatal; a notice is useful.
M device/device_util.c
Add string creation for PCI_BUS nad LPC.
M northbridge/intel/i440bxemulation/dts
Add ID info for the chip.
M northbridge/intel/i440bxemulation/i440bx.c
Change initialization so it is explicitly for the .ops struct member.
M util/dtc/flattree.c
Add support for the new path naming scheme.
I'm in the middle of this commit so I'll fix the hard-coded lengths
next commit.
Also delete dead code between #if 0 and /* and //
M util/x86emu/vm86.c
comment out unused variables. these may someday be use, not ready
to delete them yet.
M Makefile
Change -O2 to -g. We need debugging on LAR far more than we need performance.
git-svn-id: svn://coreboot.org/repository/coreboot-v3@593 f3766cd6-281f-0410-b1cd-43a5c92072e9
from v2 to install them. Linux boots fine and all interrupts
seem to work correctly -- the network comes up, USB hot plug works,
I can mount the USB disk, etc.
To enable pirq tables for a given mainboard, simply add the
select PIRQ_TABLE (see below) to the Kconfig for that board.
Again, this code builds and boots linux on the alix1c.
I think, with this change, we are very close to moving ALL LX boards to
v3 and deprecating v2. The major remaining fix is to add an empty LAR
entry to fill empty space in LAR and speed up the LAR file search
process.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Index: include/tables.h
Add prototype, conditioned on CONFIG_PIRQ_TABLE
Index: util/x86emu/vm86.c
Comment out 'debug trap' code that scribbles vectors at 0x4000.
I don't know why this is here, but I'd like to leave it #if'ed out --
somebody, at some point, thought we needed it. To reenable, we will need
to move stage2 code or these magic vectors.
Index: arch/x86/Makefile
Add support for conditional compilation of pirq support code.
Index: arch/x86/pirq_routing.c
Add this file from v2.
Index: arch/x86/archtables.c
Add call to write_pirq_routing_table (controlled by #ifdef
CONFIG_PIRQ_TABLE)
Index: arch/x86/Kconfig
Add new config variable: PIRQ_TABLE
Index: device/device.c
Fix some trivial bugs.
Index: mainboard/pcengines/alix1c/Makefile
Add pirq table code for stage2
Index: mainboard/pcengines/alix1c/dts
Modify dts to properly set southbridge variables
Index: mainboard/pcengines/alix1c/irq_tables.c
Add code from v2 for the alix1c.
Index: mainboard/pcengines/Kconfig
Add 'select PIRQ_TABLE'
Index: include/arch/x86/pirq_routing.h
Add include file from v2.
Remove all the SLOTCOUNT nonsense. This hack was only needed
for a very early version of gcc 3.x, where they screwed up the
creation of struct members that used the [] syntax for variable-length
array at the end of the struct.
Index: include/device/pci.h
Add prototype
git-svn-id: svn://coreboot.org/repository/coreboot-v3@582 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@581 f3766cd6-281f-0410-b1cd-43a5c92072e9
them just use the default.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@579 f3766cd6-281f-0410-b1cd-43a5c92072e9
released new-model VSA code.
Changes:
Index: util/dtc/flattree.c
Add an ID entry for apic properties.
Index: northbridge/amd/geodelx/apic
This is a new dts for the northbridge used as an APIC.
Index: northbridge/amd/geodelx/pci
This is a new dts for the northbridge used as a PCI device.
Index: northbridge/amd/geodelx/geodelx.c
Fix a non-obvious bug: we had set phase3 scan bus for both the
domain AND the PCI device, which is a mistake: can't scan from the
PCI device too.
Index: northbridge/amd/geodelx/domain
This is a new dts for the northbridge used as an pci domain.
Created via svn move dts domain
Index: device/pci_device.c
If there are leftover devices, it is now a warning, not an error,
since there are
some no-pci devices in the tree now. For future: only complain about
leftover PCI devices ...
Index: device/device.c
make devcnt a global and initialize it in init_dev. Add a debug printk.
Index: mainboard/pcengines/alix1c/dts
Add an 'apic' entry for the mainboard. This actually looks pretty clean
to me, the way it went in.
Index: northbridge/amd/geodelx/vsmsetup.c
Delete all pcibios int support, no longer needed for VSA.
Please note that this patch includes Carl-Daniel's improvements
below, which I have Ack-ed.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
A few minor comments. It would be great if you could address them before
committing.
northbridge/amd/geodelx/domain is a copy of northbridge/amd/geodelx/dts.
You probably want to use "svn mv" for that because it preserves history
and the old file was probably intended to have been moved, not copied.
northbridge/amd/geodelx/vsmsetup.c:247: warning: ‘biosint’ defined but
not used
Since the new VSA does not use BIOSINT services anymore, deleting
biosint and related functions from vsmsetup.c would shrink vsmsetup.c by
one fourth. Patch follows (could you merge it into your patch?):
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@571 f3766cd6-281f-0410-b1cd-43a5c92072e9
- I left LB_TAG_ intact because they are used by the payloads
- file renames are still missing. see next commit
- some lb_ renames might be missing. feel free to provide patches.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@564 f3766cd6-281f-0410-b1cd-43a5c92072e9
Remove old vendor,device struct members since we are now using the
device_id struct.
Change declaration of dev_find_device to use device_id struct.
device/device_util.c
Change dev_find_device to use device_id struct instead of vendor, device
parameters.
Add convenience function, dev_find_pci_device, to make it easier for
users.
device/pci_device.c
Change uses of dev->vendor and dev->device to dev->id.
Change prints of dev->vendor, dev->device to use the
dev_id_string function.
device/pci_rom.c
Change uses of dev->vendor and dev->device to dev->id.
southbridge/amd/cs5536/cs5536.c
Change uses of dev_find_device to dev_find_pci_device
southbridge/amd/cs5536/dts
Add pciid of the cs5536
northbridge/amd/geodelx/dts
add pciid of the geodelx northbridge.
util/x86emu/vm86.c
Change uses of dev_find_device to dev_find_pci_device
With these changes, the chipsetinit function now finds the southbridge
in the static tree, which is the first time this has worked in v3.
This success in turn means that the chipsetinit code is running for the
first time.
We are still failing in "Finding PCI configuration type"
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@558 f3766cd6-281f-0410-b1cd-43a5c92072e9
Change the ID constants so they are more useful for debugging.
Instead of simple 1,2,3 they now are a 4-byte value which can be more
useful when looking at memory with a debugger. Lots of variables can be
'1', but fewer variables will match to 'PCID'.
include/device/pci.h:
Include pci_ids.h in pci.h
device/device.c: remove silly comment. Change memcpy to struct assign, this makes it possible
for the C compiler to do type checking. Add assign for the dev->id.
flattree.c: Support the use of 'domainid' and 'pciid' in the per-chip dts. These IDs will be assigned
to the static tree device struct. In conjunction with the earlier patch, this change removes the need
for users to assign the ops struct member in the dts by hand, as it is done in the qemu port today.
The ops struct member will automatically be assigned by the dev_init function, which is run
in stage2 before any actual device code is run. (This change to dev_init was in the previous patch).
Added two comments that document what is going on.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@557 f3766cd6-281f-0410-b1cd-43a5c92072e9
I just uncovered this problem while trying to get the lx going.
The symptom was that the northbridge ops were never getting run,
in particular the phase 2 ops for the geodelx were not running. The
reason was that the ops struct member for the device was not set.
How is the ops struct member set?
Currently, the ops vector for a static device (i.e. a device created from the
dts) has to be set by hand, as in mainboard/emulation/qemu-x86/dts:
domain0 {
/config/("northbridge/intel/i440bxemulation");
ops = "i440bxemulation_pcidomainops";
This requirement is ridiculous (it's my fault). If we know the part,
and have the dts, we should not have to explicitly name the ops. In fact the
constructors array, defined at the end of the various device files, makes
searching for an ops struct for a dynamic device automatic. We should
support this automatic behavior for static devices too.
Given the function find_constructor
in device/device.c, why don't we just use that? The problem is that we did
not set up the device struct to include a device id, just a device path, and
find_constructor requires a device_id -- which makes sense, I hope,
as the path is its pci path (e.g. 0:1.0) and the constructors are defined by the
device id (i.e. it is the same constructor for a given part, no matter how many
of the part we have).
So, as a start to fixing this limitation (this is going to take several patches),
I've done the following:
1. add a struct device_id to the device struct.
2. extended the dev_init code in device/device.c -- this is the first function
called from lib/stage2.c -- to find a constructor for the dev->id and, if
found, set dev->ops to it.
Result: for static devices with the id set, the ops pointer will be set
automatically. Coreboot builds fine with this change.
The next change will be to add dtc commands to set ids.
Currently, we have commands like pcipath, pcidomain, etc.;
the new commands will look like pciid, domainid, etc. Once we have these
commands, we will have made it possible to set ops automatically. We
can just set the ids in the device dts file, and users will never have to
see any of this complication.
The final change will be a bit more complicated. Right now, if you look in,
e.g., northbridge/amd/geodelx/dts, you'll see that we have one dts, but
the northbridge plays three roles. We can't easily contain those three
roles in one dts (I am open to suggestions showing I am wrong).
I am going to propose that we have more than one dts file
in a directory, so instead of
northbridge/amd/geodelx/dts
we would have
northbridge/amd/geodelx/dtsdomain
northbridge/amd/geodelx/dtsapic
northbridge/amd/geodelx/dtspci
so that we could set the variables for each of these individual components.
There is no need to split geodelx.c into three .c files, however.
Finally, I will be removing the archaic vendor and device unsigned's from
the device struct in future, but as I say, I am trying to stage these changes
to keep them understandable.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@556 f3766cd6-281f-0410-b1cd-43a5c92072e9
numeric constants and #defines for such constants. Since grepping the
tree shouldn't be necessary to find a POST code and we already have
too many duplicated POST codes, gather almost all of them in a common
header file.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@549 f3766cd6-281f-0410-b1cd-43a5c92072e9
if the stored and calculated checksum differ.
There is no easy way to check extension ROMs in the current machine for
correct signatures, but you could copy out the memory between 0xc0000 -
0xf00000 from /dev/mem and search for extension headers in it (see the
code in pci_rom.c).
Signed-off-by: Alex Beregszaszi <alex@rtfs.hu>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@532 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@519 f3766cd6-281f-0410-b1cd-43a5c92072e9
an artifact from the time when we needed stage2 phase 1 code to make
printk work.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@512 f3766cd6-281f-0410-b1cd-43a5c92072e9
