Phase 1: done
Phase 2: early setup ...
Phase 2: done
Phase 3: Enumerating buses...
qemu-x86 enable_dev done
dev_phase3_scan: scanning Root Device
scan_static_bus for root(Root Device)
cpus: Unknown device path type: 0
cpus() enabled
i440bxemulation_enable_dev:
i440bxemulation_enable_dev: DONE
northbridge_intel_i440bxemulation() enabled
northbridge_intel_i440bxemulation() scanning...
dev_phase3_scan: scanning
pci_scan_bus start
PCI: pci_scan_bus for bus 00
PCI: scan devfn 0x0 to 0xff
PCI: devfn 0x0
PCI: pci_scan_bus pci_scan_get_dev returns dev <NULL>
Change dts compiler to emit a new struct member, dtsname, for devices,
so we can get actual useful names for things.
Several mods and printks added.
printk(BIOS_SPEW
gives no output for reasons I don't understand.
Next in line is bringing back v2 support for pci, but not doing it the
way v2 does it.
note the cpus() printk above. cpus don't have a valid path yet.
We still need to work out the dts syntax for systems with multiple links
(opteron)
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@163 f3766cd6-281f-0410-b1cd-43a5c92072e9
both dest and src are long aligned or have the same offset from being long
aligned.
memcpy() and memmove() use the helper, memmove() will properly handle dest
and src overlapping.
Update comments to reflect the code changes.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@162 f3766cd6-281f-0410-b1cd-43a5c92072e9
If this is a hard OFW limitation, let's fix OFW.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@161 f3766cd6-281f-0410-b1cd-43a5c92072e9
Also added comments.
A big change is in the dts. In OFW trees, the hierarchy seems to be:
/root/cpu/northbridge
south
other pci
note that the north is in the hierarchy under the south. This hierarchy
makes no sense on systems with a shared frontside bus, or at least I
don't see how it can. In those systems, it's easier to think about
the CPUs AND northbridges as children of the front side bus.
in LinuxBIOS, it has always been this:
/root/cpu/whatever
/root/northbridge/
south
other pci
There have been many discussions over how it ought to be, for 8 years
now, and we've always come back to how LB does it. So I have changed the
dts for qemu for now to match LB's way of doing things. Note that the
new system is flexible enough that, on K8, we CAN do things as above:
/cpu@0/amd8knorthbridge/etc.
/cpu@1/amd8knorthbridge/etc.
But on qemu, for now, the root is the mainboard, and the CPU and
northbridge are siblings.
I've added some informational printks, cleaned up pci_ops, and done
other things so that it builds and all seems to work -- until it hangs
hard in enumeration in i440bx ...
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@160 f3766cd6-281f-0410-b1cd-43a5c92072e9
use (in modified form). Add date to the versions, so we know how old
our incorporated version of the code is (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@159 f3766cd6-281f-0410-b1cd-43a5c92072e9
Not yet finished, more to come.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@158 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@157 f3766cd6-281f-0410-b1cd-43a5c92072e9
terms of the GPL, version 2.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@156 f3766cd6-281f-0410-b1cd-43a5c92072e9
Some minor cosmetic fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@155 f3766cd6-281f-0410-b1cd-43a5c92072e9
are undefined (trivial).
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@151 f3766cd6-281f-0410-b1cd-43a5c92072e9
Plus some small trivial reformatting of comments in stage0_i586.S
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@146 f3766cd6-281f-0410-b1cd-43a5c92072e9
* exchange [u]intXX_t with [us]XX types as we agreed upon.
* drop unneeded btext.h for now
* fix license header in device/pci_ops.c
* fix printk in device/pci_ops.c
* add signed types to arch/types.h
* fix include/elf.h (remove glibc-ism)
* add appropriate copyright notice to lib/delay.c
* add pciconf.h header
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@144 f3766cd6-281f-0410-b1cd-43a5c92072e9
discussion. There was obviously an earlier version by Eric which I have
not looked at before writing thios one. See rev 2131 in v2.
Trivial, thus self-acked.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@140 f3766cd6-281f-0410-b1cd-43a5c92072e9
renamed the phase3 etc. to stuff like phase3_scan, so you can get a
rought idea what it is. The names mean more.
adding pci_device and, at the same time, showing how we can get rid of
the really ugly stuff that crept in. note you can specify ops in the
dts, which avoids the need for hideous stuff like this:
static void enable_dev(struct device *dev)
{
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
dev->ops = &pci_domain_ops;
pci_set_method(dev);
}
else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
dev->ops = &cpu_bus_ops;
}
}
So that foolishness is gone.
added delay functions.
Note that we have include/lib.h, and define all the functions in there,
instead of in lots of fiddly includes.
Brought back the enable op, once I understood it; renamed it to
something that makes sense.
I'll be on a plane soon, will continue to work, but at least you can see
what's going on here.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@139 f3766cd6-281f-0410-b1cd-43a5c92072e9
because not all emulators get the ram size registers right, or so we
hear.
This northbridge is still incomplete. We are not just copying the v2
one, as we are trying to undo the various hacks that crept in over the
years, due to limitations in the v2 device model. Just look at the
i440bx in v2 and you can see what I mean. We are working to find a
better way to get the job done than those hacks. They are just too
confusing for people to follow.
add an include for the northbridge makefile into the qemu Makefile.
Re-order the includes in arch/x86/Makefile so we can pick up .o files
from other places. Add a STAGE2_CHIPSET_OBJ for objects defined in those
makefiles included in mainboard.
Current issues: the enable_dev function for the i440bx is not getting
called. Enable_dev should be renamed to phase3_setup or something that
actually means something. The name as it is is totally useless.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@138 f3766cd6-281f-0410-b1cd-43a5c92072e9
more comprehensible. tested on bochs.
Some documentation on what is going on in stage2
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@136 f3766cd6-281f-0410-b1cd-43a5c92072e9
start documenting the device model -- since it is clear to me from
reading v2 that not even the v2 guys totally got it
call write_tables in stage2
fix the makefile to put stage2.o first to make sure it gets
called.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@135 f3766cd6-281f-0410-b1cd-43a5c92072e9
I was meaning to check in more, but I lost 4h of work due to some ext3
problem. Bummer I believed those saying its more stable than reiserfs.
Signed-off-by: Stefan Reinauer <stepan@openbios.org>
Acked-by: Stefan Reinauer <stepan@openbios.org>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@134 f3766cd6-281f-0410-b1cd-43a5c92072e9
Remaining to be done:
PIRQ table
MP table
ACPI table
relocate the GDT reload to a sensible place -- or figure out if we even
need to bother; we're back to execute in place and the GDT is in flash
rom ==> we can leave it until we boot the payload I think.
At this point, however, we've got the basic bits to sensibly create
tables.
This has been tested and works on bochs.
It is working to a point, but still failing on qemu for reasons we don't
quite understand.
Elfboot
Found ELF candidate at offset 0
New segment addr 0x100000 size 0x21310 offset 0xc0 filesize 0x7348
(cleaned up) New segment addr 0x100000 size 0x7348 offset 0xc0
set 00100000 to 0 for 0 bytes
Copy to 00100000 from fffc3f24 for 29512 bytes
New segment addr 0x121320 size 0x48 offset 0x7420 filesize 0x48
(cleaned up) New segment addr 0x121320 size 0x48 offset 0x7420
set 00121320 to 0 for 0 bytes
Copy to 00121320 from fffcb284 for 72 bytes
Dropping non PT_LOAD segment
Dropping non PT_LOAD segment
Jumping to boot code at 0x1047c0
FILO version 0.5 (rminnich@q.ccstar.lanl.gov) Sun Feb 25 10:19:16 MST
2007
collect_sys_info: boot eax = 0xfe
collect_sys_info: boot ebx = 0xffffd4ca
collect_sys_info: boot arg = 0x1047c0
collect_linuxbios_info: NOT Searching for LinuxBIOS tables...
Can't get memory map from firmware. Using hardcoded default.
collect_sys_info: 0000000000000000-00000000000a0000
collect_sys_info: 0000000000100000-0000000002000000
collect_sys_info: RAM 32 MB
relocate: Current location: 0x1000c7-0x12142e
relocate: Relocating to 0x1fdec90-0x1fffff7... ok
Press <Enter> for default boot, or <Esc> for boot prompt...
boot: hdc1:/phase1 root=/dev/hdc1 console=ttyS0,115200
malloc_check: invalid head->prev_size: 0x0
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@133 f3766cd6-281f-0410-b1cd-43a5c92072e9
resource .c functions -- sigh -- this will be next.
fix types, fix some usage, but we do not yet generate pirqi, mptables,
or acpi. This will be next.
This code will be called from phase6 in stage 2, and probably
attached to a cpu. Or, it will be inline in the stage2.c code, since
the need for tables is generic.
I'm also going to move the cryptic usage of lgdt from here to stage 2,
phase 2, of the cpu code. The device model improvements are making it
easier to think about when things happen, we are finding.
I'm going to get lunch and go see some of brussels. It's a miserable day
but ...
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@130 f3766cd6-281f-0410-b1cd-43a5c92072e9
commit. adding support for tables.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@129 f3766cd6-281f-0410-b1cd-43a5c92072e9
We have merged the plethora of include files into one. A given linuxbios
target architecture must support all the functions described therein.
All the structs etc. in include/tables.h are known to be
architecture-independent.
We hope this new layout is easier to folow than the old one.
Todo: Remove the LGDT code from tables writing (how did THAT get in
there ;-) and put it somewhere sane; add OFW table support. We are going
to need some nice OFW table code.
Also, the license headers should be correct in this commit.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@128 f3766cd6-281f-0410-b1cd-43a5c92072e9
warnings for developing/debugging, but not for the default LinuxBIOS build.
These are purely cosmetic changes, no build process changes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@126 f3766cd6-281f-0410-b1cd-43a5c92072e9
understood. This file has been tested and works with FILO 0.5.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@123 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@121 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@120 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@119 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@118 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@117 f3766cd6-281f-0410-b1cd-43a5c92072e9
