Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@938 f3766cd6-281f-0410-b1cd-43a5c92072e9
I did change the /bin/bash to /bin/sh per the comments.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@919 f3766cd6-281f-0410-b1cd-43a5c92072e9
multiple links. The way this was done in v2 was a big confusing; this way is
less so.
The changes are easy. Getting them right has been hard :-)
First, for a k8 north that has three links, you can name each one as follows:
pci0@18,0
pci1@18,0
pci2@18,0
We have to have the same pcidevfn on these because that is how the k8 works.
But the unit numbers (pci0, pci1, etc.) distinguish them.
The dts will properly generate a "v3 device code"
compatible static tree that puts the links in the right place in the
data structure.
The changes to dts are trivial.
As before, dts nodes with children are understood to be a bridge.
But what if there is a dts entry like this:
pci1@18,0 {/config/("northbridge/amd/k8/pci");};
This entry has no children in the dts.
How does dt compiler know it is a bridge? It can not know unless
we add information to the dts for that northbridge part.
To ensure that all bridge devices are detected, we support the following:
if a dts node for a device has a bridge property, e.g.:
{
device_operations = "k8_ops";
bridge;
};
The dt compiler will treat it as a bridge whether it has children or not.
Why would a device not have children? Because it might be attached to a
pci or other socket, and we don't know at build time if the socket is empty,
or what might be in the socket.
This code has been tested on dbe62 and k8 simnow, and works on each.
It is minimal in size and it does what we need. I hope it resolves our
discussion for now. We might want to improve or change the device code
later but, at this point, forward motion is important -- I'm on a deadline for
a very important demo Oct. 22!
Also included in this patch are new debug prints in k8 north.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@865 f3766cd6-281f-0410-b1cd-43a5c92072e9
dtc only uses dev_fn as identifier for a PCI device. That gets us a name
collision if we have the same dev_fn combination on multiple buses.
Either we add a random unique ID to the struct name or we integrate the
path to the parent device as well.
I decided to go for integration of parent device path.
With the following device tree
/{
cpus {};
domain@0 {
bus@0 {
pci@0,0 {
};
pci@1,1 {
};
pci@f,0 {
bus@1 {
pci@0,0 {
};
};
};
};
};
};
we get the old names:
dev_root
dev_cpus
dev_domain_0
dev_bus_0
dev_pci_0_0
dev_pci_1_1
dev_pci_f_0
dev_bus_1
dev_pci_0_0 COLLISION!!!
and the new names:
dev_root
dev_cpus
dev_domain_0
dev_domain_0_bus_0
dev_domain_0_bus_0_pci_0_0
dev_domain_0_bus_0_pci_1_1
dev_domain_0_bus_0_pci_f_0
dev_domain_0_bus_0_pci_f_0_bus_1
dev_domain_0_bus_0_pci_f_0_bus_1_pci_0_0
Ron would like shorter names because they only have to be
machine-readable. That's left for another patch.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@860 f3766cd6-281f-0410-b1cd-43a5c92072e9
Fix the bus location for Qemu IDE.
This patch only provides the needed infrastructure for per-device
subsystem IDs, it does not hook them up to the PCI core yet, so this
patch is a no-op.
By the way, the on_mainboard property is activating lots of completely
untested code paths in v3, so someone might want to audit them.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@844 f3766cd6-281f-0410-b1cd-43a5c92072e9
Now to start testing.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@810 f3766cd6-281f-0410-b1cd-43a5c92072e9
few hardcodes introduced with my checker.
Tested on Linux and OSX.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@798 f3766cd6-281f-0410-b1cd-43a5c92072e9
simply hope they are unused/empty and will get runtime crashes/
corruption/malfunction if they are not empty. Same applies to any
sections with relocation entries which can not be resolved during
link time.
Check for the emptiness of these sections and abort the build on error.
This triggers on all stage1/initram global variables which are not
declared the right way. It also triggers on local static variables.
Features of this checker:
- It doesn't only check for non-empty .data and .bss, but also for
unknown sections which would be a problem.
- It gives you the offending filename, the section and the variable
name.
- It won't stop after the first error and will tell you about all errors
for a given file list.
This found a long-standing bug introduced in r729 and fixed in r786.
It also broke the build of every Geode target in the v3 tree because
they had multiple bugs. And it broke the build of the K8 code because
of a bug there.
Other fixes resulting from this checker are in r790 and r791.
Ron already fixed some of the bugs uncovered by this checker.
Tested for all possible variations of .data and .bss usage.
Sample output follows:
CC build/coreboot.initram (XIP)
CHECK initram (non-empty writable/allocatable sections)
build/coreboot.initram_partiallylinked.o: section .data: foo1
build/coreboot.initram_partiallylinked.o: section .bss: foo2
build/coreboot.initram_partiallylinked.o: section .data.rel.ro.local:
msrnames.2746
make: *** [build/coreboot.initram] Error 1
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Segher Boessenkool <segher@kernel.crashing.org>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@794 f3766cd6-281f-0410-b1cd-43a5c92072e9
Also gets rid of hard-codes in fwrite for strings that might, in future,
vary.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@791 f3766cd6-281f-0410-b1cd-43a5c92072e9
Calling non-PIC code from PIC code needs an ABI wrapper and we don't
provide one. Our trick with function pointers is exceedingly fragile:
- it depends on gcc not being clever enough
- it forces us to compile all initram source files in one go
- parallelizing initram compilation breaks the code
- compiling one initram source file at a time breaks the code
- enabling higher optimizations breaks the code
- enabling -fwhole-program breaks the code
- declaring the function pointers const breaks the code
- it's an undocumented side effect of gcc which will go away
- we need excessively ugly shared function wrappers
- the shared function wrappers had more than their fair share of bugs
- almost nobody understands the wrappers completely
- Segher warns against them: "So why do you think this should work?
You're telling it to link PIC to non-PIC. Did you read the manual? It's
just not allowed. It cannot ever work."
Kill the SHARED wrappers and use a real ABI wrapper.
The wrapper code is autogenerated on demand.
Any function compiled into stage0 is now shared by default, yet the size
and code generation of stage0/1/2 code are unchanged. Initram code size
does decrease quite a bit and the difficulty of creating shared
functions is now zero.
The patch includes extensive documentation about the inner workings of
the new wrappers and the reasons why they look like this.
Build and boot tested on qemu.
Build tested on all targets.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Ron says:
Wow. we've need this fix for a long time.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@775 f3766cd6-281f-0410-b1cd-43a5c92072e9
Basically, anything that includes files from include/ should define
STANDALONE, so that the includes don't try to created SHARED symbols.
This was not a problem until we made get_option SHARED.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@755 f3766cd6-281f-0410-b1cd-43a5c92072e9
This is managed by stripping the .dtc from the name when it
is used to label the node in the tree.
This one's for you Peter!
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@740 f3766cd6-281f-0410-b1cd-43a5c92072e9
readability. Move to anonymous unions.
Build tested on all targets. Boot tested on qemu.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Ron tested this and it boots to Linux.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@730 f3766cd6-281f-0410-b1cd-43a5c92072e9
2. Fix trivial bug in dtc -- ioport is 6 chars long, not 3
3. Fix all dts so that the @ parts are now in hex.
4. fix graphics mem in dbs62 to be 16 MB, per artec.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@700 f3766cd6-281f-0410-b1cd-43a5c92072e9
is the logical continuation of r416 which happened a year ago.
As an added bonus, we now have consistent naming again, making grepping
the source for dts properties possible.
Build tested on all targets. Patch attached for Gmail users.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@697 f3766cd6-281f-0410-b1cd-43a5c92072e9
mainboard-name naming has been postponed because it's not clear what the
real name should be.
Generated code is identical to the state before the patch.
Compile tested.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@694 f3766cd6-281f-0410-b1cd-43a5c92072e9
Compile tested including boundary cases.
Runtime tested on dbe62 by Ron. Works fine.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@693 f3766cd6-281f-0410-b1cd-43a5c92072e9
building kconfig and lxdialog, so that their
content is used to resolve unknown symbols even
when they are static libraries.
Also fix HOST_LOADLIBS typo.
Signed-Off-By: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@690 f3766cd6-281f-0410-b1cd-43a5c92072e9
This makes doxygen documentation building work again.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@683 f3766cd6-281f-0410-b1cd-43a5c92072e9
This program was originally written for OLPC and GX, and dumps all LX
registers used in coreboot.
I have preserved the indent structure since that gives some idea of the
scope of variables.
Of particular interest are the GLD variables, since they are always
listed as offsets in the manuals,
and computing the actual number (for use in rdmsr etc.) can be really
tricky.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@681 f3766cd6-281f-0410-b1cd-43a5c92072e9
Thanks to Carl-Daniel for spotting this one, and Segher for providing the solution right away.
This is a trivial patch.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@667 f3766cd6-281f-0410-b1cd-43a5c92072e9
This is necessary for the 'unwanted_vpci' field on geode-based boards.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@661 f3766cd6-281f-0410-b1cd-43a5c92072e9
It also fixes lzma compression in lar to fix the silent memory
corruption that was possible when files didn't compress well.
It adds some comments to both files and the file that calls them.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@658 f3766cd6-281f-0410-b1cd-43a5c92072e9
LAR archive, the LAR utility will segfault. This is reproduced easily by
zerofilling the LAR, then adding anything to it.
Looking at the code, the reason is obvious:
lar_empty_offset() can return an error code (-1). None of the callers
check for an error code, they simply assume the return value is valid.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@647 f3766cd6-281f-0410-b1cd-43a5c92072e9
makes use of functions that were already defined. It also adds greedy name
matching for listing and extracting archives, which allows recursive descent
into the lar directory structure.
changes file-by-file:
util/lar/lar.c:
add more options to the usage message
use get_larsize() instead of using larsize
rearrange errors from parsing args to be more correct
util/lar/stream.c:
change elfname size to MAX_PATHLEN instead of 64
make file_in_list greedy with filename matches
change total_size calculation to include file names
change lar_add_entry to use header_len function instead of reinventing
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@632 f3766cd6-281f-0410-b1cd-43a5c92072e9
file struct for pathname and compression, so that directories can be correctly
recursed.
file-by-file:
util/lar/lar.c:
make error messages more verbose
pass a pointer to the file structure instead of the name
parse the name here with lar_process_name
util/lar/lib.c:
change handle_directory to use a path name and respect nocompress
change add_files to use pre-processed names
use sensible defaults for new file members when listing or extracting
free pathname if allocated
util/lar/lib.h:
add new members to struct file
change prototypes of add_files and lar_add_file
util/lar/stream.c:
change lar_add_file to use pathname and compression from struct file
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@623 f3766cd6-281f-0410-b1cd-43a5c92072e9
(makes it the same as create.)
Without this patch you can create a lar and recursively add a
directory to it, but you can't add one with add.
Another patch might be to make lar -l print something when you use the
directory option, but I'm not sure what was intended originally.
Myles
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@618 f3766cd6-281f-0410-b1cd-43a5c92072e9
file is not found instead of seg faulting.
test with:
lar -a coreboot.rom nonexistant_file.bin
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@615 f3766cd6-281f-0410-b1cd-43a5c92072e9
Carl-Daniel Hailfinger wrote:
> On 18.02.2008 23:55, Marc Jones wrote:
>> Carl-Daniel Hailfinger wrote:
>>> it seems that executing VSA requires vm86 to be useful. Since we
>>> unconditionally execute the VSA, we should unconditionally require
vm86
>>> support (PCI_OPTION_ROM_RUN_VM86) via Kconfig for Geode targets. Not
>>> doing so will either cause compile failures or runtime failures.
>>>
>>> Adding
>>> select PCI_OPTION_ROM_RUN_VM86
>>> below
>>> config CPU_AMD_GEODELX
>>> did not work out for me.
>> Sorry I missed this.
>>
>> VSA requires the GDT that is in vm86.c. VSA loads similar to an
option
>> ROM so the loader does go into VM86 mode. All the other stuff like
>> interrupt support and PCI BIOS isn't needed by VSA. I think that the
>> GDT at the top of vm86.c can be moved to a header file, gdt.h or
>> something like that.
>
> northbridge/amd/geodelx/vsmsetup.c uses
> util/x86emu/vm86.c:setup_realmode_idt() but it seems most/all of the
> setup there is not needed at all for VSA. Pulling in
setup_realmode_idt
> pulls in the rest of vm86 through direct and indirect dependencies.
>
>> Care to make a patch? :)
>
I am also leaning towards removing the IDT for VSA init. There is a risk
if either an exception happens or a software interrupt is used you will
get unexpected results. What probably happens is that you jump off to
something that will eventually cause a triple fault and reboot. You may
think this is bad (and it is) but it is the same risk that coreboot runs
today. If coreboot had a generic IDT to handle exceptions, VSA init
would use the same IDT. Note that hardware INT (even timers) should
never happen as they are always masked.
I have built with no PCI_OPTION_ROM_RUN_VM86 and run this to filo.
- Show quoted text -
Marc
--
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones@amd.com
http://www.amd.com/embeddedprocessors
Reduce the amount of compilation errors for Geode LX targets if x86emu
or no emulation is selected instead of vm86.
Factor out GDT code from vm86.c to vm86_gdt.c
Remove IDT setup for VSA init.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-of-by: Marc Jones <marc.jones@amd.com>
This has booted to runlevel 3 and the ethernet works fine.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@613 f3766cd6-281f-0410-b1cd-43a5c92072e9
> > Author: rminnich
> > util/x86emu/vm86.c
> > Change uses of dev_find_device to dev_find_pci_device
Unfortunately, x86emu/pcbios/pcibios.c was missed in the conversion. Fix
it to get builds with x86emu compiling again.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@612 f3766cd6-281f-0410-b1cd-43a5c92072e9
number during boot.
Convert process_file() to use enum compalgo instead of hardcoded
"1","2","3" and change the control structure from a series of if()
statements to a switch() statement.
Uppercasing enum compalgo also found a name clash between NONE as
compression algo and NONE as operation mode of util/lar.
Compile and boot tested on Qemu.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@606 f3766cd6-281f-0410-b1cd-43a5c92072e9
> Alix1c won't boot with the zero decompress code.
> I think the code is using the wrong address on decompress.
Indeed, r601 broke all targets, you were just lucky that qemu didn't
explode as well.
It's the seemingly easy patches which break booting. With your hint, I
found the bug. Myles made a small, but important mistake with the memset
for the "zeroes" decompression.
The memset zeroed the archive instead of the destination. No wonder it
did explode.
This patch fixes it and also reverts the emergency commit r604 because
that one is no longer necessary.
Ron tested on the Alix1c, boots fine, ethernet and IDE working.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@605 f3766cd6-281f-0410-b1cd-43a5c92072e9
it stands, is causing coreboot on the alix1c to hang. I don't know why.
But this patch is the difference between works and hangs. I think
the memset in the decompress is not using the right start value? Not sure.
This simple change allows us to fix the zero decompress later, when
we figure it out. I just lost a few hours to this and I want to make
sure the repo works before I go to bed.
This fix tested on alix1c. Alix1c now works fine.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@604 f3766cd6-281f-0410-b1cd-43a5c92072e9
code boots and works on qemu and
alix1c. It represents a huge change and a huge improvement. There are a
few fixes left to do, which
will come once this is in.
This change started out easy: get the device IDs OUT of the the dts, and
into one place. We
decided the device IDs should be in the constructors ONLY. To make a
long story short, that just did
not work out, and it revealed a flaw in the design. The result?
- no more ids in the various dts files.
- the constructor struct is gone -- one less struct, nobody liked the
name anyway
- the device_operations struct now includes the device id.
- constructor property no longer used; use device_operations instead.
- lpc replaced with ioport
All the changes below stem from this "simple" change.
I am finding this new structure much easier to work with. I hope we're
done
on this for real, however!
TODO:
1. Change limitation in dtc that makes it hard to use hex in pci@
notation.
Now for the bad news. Sometime today, interrupts or io or something
stopped working between r596 and r602 -- but I did no commits at
that point. So something has gone wrong, but I don't think it's this
stuff.
I did try a build of HEAD, and it fails really, really badly. Much
more badly than this fails, so I think this commit is only going
to improve things. It does work fine on qemu, fails on alix1c,
so I suspect one of today's "clean up commits" broke something.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@603 f3766cd6-281f-0410-b1cd-43a5c92072e9
for this is that currently, if you select no compression, the bss
segment of filo takes up 153K with just zeroes. With this patch, it
always takes up a lar header + 1 byte. I left the one byte so that
the checksum wouldn't be broken.
This patch could have taken out the calloc in the compression area,
but since it only uses compile-time memory, I decided to keep this
simple.
Myles
Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@601 f3766cd6-281f-0410-b1cd-43a5c92072e9
buffer overflow checks. It exits with an error instead of
overflowing.
Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@594 f3766cd6-281f-0410-b1cd-43a5c92072e9
in dts. This gets rid of the ugly pcipath etc. properties.
So, instead of
somedevice {pcipath="1,0";};
We say pci@1,0{ etc. etc. };
As per my agreement I agree to document this in the design doc.
The alix1c compiles but is untested, and will probably need some work.
I will do these additional tasks on friday.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
M include/device/path.h
Add LPC path type, replacing SUPERIO path type, since SUPERIO is only
one type of LPC. Clean up tabbing in parts of the file (cosmetic).
M mainboard/emulation/qemu-x86/dts
Modify this dts for the new path naming scheme.
M device/pci_device.c
Change what used to be a BIOS_ERR (but is no longer) to a BIOS_NOTICE.
The change is that the device tree includes more than just PCI devices,
so finding a non-PCI device is no longer fatal; a notice is useful.
M device/device_util.c
Add string creation for PCI_BUS nad LPC.
M northbridge/intel/i440bxemulation/dts
Add ID info for the chip.
M northbridge/intel/i440bxemulation/i440bx.c
Change initialization so it is explicitly for the .ops struct member.
M util/dtc/flattree.c
Add support for the new path naming scheme.
I'm in the middle of this commit so I'll fix the hard-coded lengths
next commit.
Also delete dead code between #if 0 and /* and //
M util/x86emu/vm86.c
comment out unused variables. these may someday be use, not ready
to delete them yet.
M Makefile
Change -O2 to -g. We need debugging on LAR far more than we need performance.
git-svn-id: svn://coreboot.org/repository/coreboot-v3@593 f3766cd6-281f-0410-b1cd-43a5c92072e9
architecture. The function prototypes had a size mismatch, which overwrote
other things on the stack. Now the prototypes use int for lengths.
Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@592 f3766cd6-281f-0410-b1cd-43a5c92072e9
