Make changes to the vendorcode files that allow them to work
with the binaryPI. This fixes various compile issues and
establishes a common calling convention between coreboot and
AGESA.
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry picked from commit f7ea2785d70bd6813b5b4d315b064802251d9557)
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17195
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: Ie36228476a9dbd7b83f95828ca9c7252cecd8ec8
Reviewed-on: https://chromium-review.googlesource.com/408967
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Make exact copies of the AGESA files from the Stoney PI package
replacing existing versions. Change the license text and fix
up misc. whitespace.
This will facilitate the review of binaryPI changes in the
vendorcode directory.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 1097249585ab76fab59dcfbf8e7a419f34fcfcb6)
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17194
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I9951df58aeab2d533efc0a837ce35f343ff28d7c
Reviewed-on: https://chromium-review.googlesource.com/408966
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add acpigen_write_opregion that generates ACPI AML code for OperationRegion,
region name, region space, region length & region size are inputs.
Add acpigen_write_field that generates ACPI AML code for Field.
Operation region name & field list are inputs.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17113
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Change-Id: I578834217d39aa3b0d409eb8ba4b5f7a31969fa8
Reviewed-on: https://chromium-review.googlesource.com/408964
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
CLK_B1(GPIO_80) and DATA_2(GPIO_83) pins needs to be
configured as native mode to use them for DMIC record
on other potential DMIC's.
DMIC blobs configure the clocks. For stereo & quad channel
record, both CLK_A1 and CLK_B1 are enabled.
For mono channel record, only CLK_A1 is enabled.
BUG=chrome-os-partner:56918
BRANCH=None
TEST=During DMIC record, check CLK_B1 and DATA_2 lines
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/17199
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I838009b85190de5360d593238e48c9593c1dc43a
Reviewed-on: https://chromium-review.googlesource.com/408962
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
A dedicated pmc_ipc DSDT entry is required for pmc_ipc kernel driver.
The ACPI mode entry includes resources for PMC_IPC1, SRAM, ACPI IO and
Punit Mailbox.
BRANCH=None
BUG=chrome-os-partner:57364
TEST=Boot up into OS successfully and check with dmesg to see the
driver has been loaded successfully without errors.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/17181
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Change-Id: Ib0a300febe1e7fc1796bfeca1a04493f932640e1
Reviewed-on: https://chromium-review.googlesource.com/408961
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
SATA device remains unrecognized if connected at Port 2.
Port control and Status register (PCS) is by default set by
hardware to the disabled state as a result of an initial
power on reset. OS read PCS register during boot causes
disabling of SATA ports and can't detect any devices.
BRANCH=none
BUG=chrome-os-partner:59335
TEST=Build and boot SKL from SATA device connected at Port 2.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/17229
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I4866ca44567f5024edaca2d48098af5b4c67a7ac
Reviewed-on: https://chromium-review.googlesource.com/408960
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Avoid use of Local0 variable in TEVT acpi method.
If mainboard doesn't expose any thermal sensor, then warning is
generated for variable Local0 not been used.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17245
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I0634961a01144e41a8480c8c6ed8b7fdd358e768
Reviewed-on: https://chromium-review.googlesource.com/408958
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Note that currently, traps are only handled by the trap handler
installed in the bootblock. The romstage and ramstage don't override it.
TEST=Booted emulation/spike-qemu and lowrisc/nexys4ddr with a linux
payload. It worked as much as before (Linux didn't boot, but it
made some successful SBI calls)
BUG=None
BRANCH=None
Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/17057
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Change-Id: Icce96ab3f41ae0f34bd86e30f9ff17c30317854e
Reviewed-on: https://chromium-review.googlesource.com/408956
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Ron's code calculated the DLL and DLM registers of the 8250 UART, but
that's the job of the UART driver. uart_input_clock_divider isn't needed
anymore because the default value of 16 works.
As a bonus, the baud rate can now be selected in Kconfig, instead of
being hardcoded at 115200.
TEST=Booted the board at 9600 and 115200 baud.
BUG=None
BRANCH=None
Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/17188
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Change-Id: I3d5e49568b798a6a6d944db1161def7d0a2d3b48
Reviewed-on: https://chromium-review.googlesource.com/408671
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Log when the MRC cache is attempted to be updated with status
of success or failure. Just one slot is supported currently
which is deemed 'normal'. This is because there are more slots
anticipated in the future.
BUG=chrome-os-partner:59395
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17231
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Change-Id: I0f81458325697aff9924cc359a4173e0d35da5da
Reviewed-on: https://chromium-review.googlesource.com/408264
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Some events were added in other places, but coreboot's
elog namespace wasn't updated. As such there's a collision
with the thermtrip event. This change at least updates the
elog information to reflect potential event type uage.
BUG=chrome-os-partner:59395
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17230
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib82e2b65ef7d34e260b7d7450174aee7537b69f6
Reviewed-on: https://chromium-review.googlesource.com/408263
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This brings the frequency down to 400kHz which is spec for
fast i2c.
BUG=chrome-os-partner:58889
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17215
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: Ibc5f152e55ed618f18ac6425264f086b1f2d1ffa
Reviewed-on: https://chromium-review.googlesource.com/408260
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This brings the frequency down to 400kHz which is spec for
fast i2c.
BUG=chrome-os-partner:58889
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17214
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I8689a062b5457aa431eaa7fb688a7170dad83fcf
Reviewed-on: https://chromium-review.googlesource.com/408259
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
1. Update gpio.h to set proper pad config for Kaby Lake RVP3.
2. Set spd index to zero.
3. Remove nhlt specific init.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17161
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I41a312d92acd2c111465a5e8f1771158e3f33e2b
Reviewed-on: https://chromium-review.googlesource.com/408257
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add support for following 3 modules.
- Micro MT52L256M32D1PF / MT52L512M32D2PF
- Hynix H9CCNNNBJTALAR
Hana EVT was planed to add 4 DRAM modules but RAM_CODE=5 is not used
in the end.
This patch also unifies the naming of the RAM configurations.
BUG=chrome-os-partner:58983
TEST=verified on Hana EVT.
Change-Id: I7c245c8c24be159e152f4f3cca25bf970b58425c
Signed-off-by: Milton Chiang <milton.chiang@mediatek.com>
Signed-off-by: PH Hsu <ph.hsu@mediatek.com>
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/402888
Reviewed-by: Pin-Huan Hsu <ph.hsu@mediatek.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paris Yeh <pyeh@chromium.org>
This was a dummy implementation until now which returned -1 always. Add
support for reading SPI flash status register (srp0).
BUG=chrome-os-partner:59267
BRANCH=None
TEST=Verified by enabling and disabling write-protect on reef that the
value of SRP0 changes accordingly in status register read.
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17205
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ib1349605dd87c4a087e416f52a8256b1eaac4f4c
Reviewed-on: https://chromium-review.googlesource.com/407195
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
After I did a new toolchain build, I found the
the mhartid register value is wrong for Spike.
The docs seem to agree with Spike, not the
code the toolchain produces?
Until such time as the bitstreams and toolchain can find
a way to agree, just hardcode it. We've been playing this game
for two years now so this is hardly a new approach.
This is intentionally ugly because we really need the
toolchains and emulators and bitstreams to sync up,
and that's not happening yet. Lowrisc
allegedly implements the v1.9 spec but it's PTEs are clearly
1.7. Once it all settles down we can just use constants
supplied by the toolchain.
I hope the syncup will have happened by the workshop in November.
This gets spike running again.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17183
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Change-Id: If259bcb6b6320ef01ed29a20ce3d2dcfd0bc7326
Reviewed-on: https://chromium-review.googlesource.com/407192
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The Stoney processor can use multiple directory structures. Turn
this feature on in the makefile.
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Tested-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry picked from commit a3334632fd53c07a046c9b23161f6ee67e5cb16e)
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17149
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Zheng Bao <fishbaozi@gmail.com>
Change-Id: I40a9ef2e6bed51bc339d3f9ae7c6f316192c4a78
Reviewed-on: https://chromium-review.googlesource.com/407191
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Double the space for psp2dir to 0x200.
Based on advice from AMD, increase the region containing
the signature to 4K.
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry picked from commit e03a9402711c3a210816d0aa32865491a0523639)
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17148
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Zheng Bao <fishbaozi@gmail.com>
Change-Id: If60132f913928bab0c2fe4aacedf342080929599
Reviewed-on: https://chromium-review.googlesource.com/407190
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The Stoney device supports only a single channel of DRAM with
two DIMMs. Correct the dimmensions of the SPD lookup array.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: <marcj303@gmail.com>
(cherry picked from commit 54a5e4a7092b77cca90894e86387f719fa3aa2c8)
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17145
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: Ib776133e411d483bb5b7e3c070199befc631d209
Reviewed-on: https://chromium-review.googlesource.com/407187
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Modify the new Stoney support files to match the APU's IDs and codename.
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry picked from commit de626730758def76e558294762a06d8ec9950cb9)
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17143
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: Idc914bc80a27ac13426fdf00fc3f578ce072086f
Reviewed-on: https://chromium-review.googlesource.com/407185
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Some user might change some devices. After a suspend this reset
to the (nvram) defaults which breaks the user expectation.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/16215
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: Ifacca35210474ec3db41a53d2ad18f3798b14077
Reviewed-on: https://chromium-review.googlesource.com/407177
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Testing for "devfn < 0" on an unsigned doesn't work, and i2c_bus_to_devfn
returns an int (with -1 for "error"), so use int for devfn.
Adapt Change-Id I7d1cdb6af4140f7dc322141c0c018d8418627434 to fix more
instances.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1357450, #1357449
Reviewed-on: https://review.coreboot.org/17054
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I001a9b484a68e018798a65c0fae11f8df7d9f564
Reviewed-on: https://chromium-review.googlesource.com/407173
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Coreboot's build system picks up the BL31 image as an ELF from the ARM
Trusted Firmware submodule and inserts it into CBFS. However, the
generic 'bl31' build target we run in the ARM Trusted Firmware build
system also generates a raw bl31.bin binary file.
We don't need that binary, and with the recently added support for
multiple non-contiguous program segments in BL31 it can grow close to
4GB in size (by having one section mapped near the start and one near
the end of the address space). To avoid clogging up people's hard drives
with 4GB of zeroes, let's only build the target we actually need.
BRANCH=gru
BUG=chrome-os-partner:56314,chromium:661124
TEST=FEATURES=noclean emerge-kevin coreboot, confirm that there's no
giant build/3rdparty/arm-trusted-firmware/bl31.bin file left in the
build artifacts, and that we still generate .d prerequisite files.
Change-Id: Iaa073ec11dabed7265620d370fcd01ea8c0c2056
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/407110
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Dumping and behavioral analysis have shown that there are more registers
in the environment control of the IT8783E/F than documented in my data-
sheet. This adds every register that wasn't 0x00/0xff by default. The
default values are guesswork: those that looked like sensor readings
became NANA, others are taken from dumps.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17005
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I7e39700c9b98ed5be9f085bc8ffd848006310254
Reviewed-on: https://chromium-review.googlesource.com/407170
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
