Commit graph

19795 commits

Author SHA1 Message Date
Jonathan Neuschäfer
d2778bb400 UPSTREAM: Kconfig: Document what ASPM means
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/17973
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: I57dd933ad70ffac95388d832bd5047f2225688e3
Reviewed-on: https://chromium-review.googlesource.com/425266
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:00:40 -08:00
Jonathan Neuschäfer
f63d01771d UPSTREAM: payloads/external: Download FILO over HTTPS
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/17972
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: I1b44e32505b96978849d39764ff399a502fa6e84
Reviewed-on: https://chromium-review.googlesource.com/425265
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:00:37 -08:00
Jonathan Neuschäfer
caafc464f3 UPSTREAM: payloads/external: Download iPXE over HTTPS
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/17971
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: Ie4979ab8491ee821b39a273c5f354c445105d2a4
Reviewed-on: https://chromium-review.googlesource.com/425264
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:00:35 -08:00
Arthur Heymans
67ff362802 UPSTREAM: mb/asus/p5gc-mx: Fix and complete SIO devicetree options
The devicetree lacks the 'chip' option for the Super I/O,
which causes the Super I/O related entries to be ignored.

This also adds other LDN that are present on this Super I/O.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17965
Tested-by: build bot (Jenkins)
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: Ida1b3c6575aa53bc7060070835c811665bdc1db1
Reviewed-on: https://chromium-review.googlesource.com/425263
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:00:33 -08:00
Paul Menzel
82651df8e2 UPSTREAM: util/intelmetool: Fix warning building with 32-bit
On a 32-bit system, pointers are 32-bit wide, and not 64-bit, resulting
in the warning below.

```
mmap.c: In function map_physical_exact:
mmap.c:26:20: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
   virt_addr = mmap((void*)mapto, len, PROT_WRITE | PROT_READ,
                    ^
```

Fix this by using compatible types.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/17970
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I4ede26127efcbd5668b978e6880a0535607e373d
Reviewed-on: https://chromium-review.googlesource.com/425262
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:00:30 -08:00
Nico Huber
e4adc5c60e UPSTREAM: buildgcc: Indicate CXXFLAGS for binutils
CXXFLAGS seems to be used a lot and have to be specified independently
from CFLAGS.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17937
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: Iff4c76e54a46e908299b532fd848165a3dc04d43
Reviewed-on: https://chromium-review.googlesource.com/425261
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:00:28 -08:00
Nico Huber
f5a0ee7a42 UPSTREAM: buildgcc: Fix string comparison operator
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17942
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I8ff8d51507dcf12cd554c8b4713074a99e47c11e
Reviewed-on: https://chromium-review.googlesource.com/425260
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:00:25 -08:00
Martin Roth
d2cc87f0e1 UPSTREAM: Microcode: Show a useful warning when microcode bins are missing
Because the binary repo is disabled by default, we get frequent
questions about why the build failed, relating to microcode in the
binary repository.

- Show an error saying that the file is missing instead of the typical
make error of no rule to build the file.
- Show a note encouraging users to try enabling the binary repo if it's
not enabled.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17940
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>

Change-Id: If4148c18cfb781ed2932bd2ae4a289b621afdebf
Reviewed-on: https://chromium-review.googlesource.com/425259
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:00:23 -08:00
Nico Huber
5e43c61461 UPSTREAM: buildgcc: Build GMP --with-pic if GCC defaults to -pie
GCC 6 can optionally default to building all binaries as position
independent executables (PIE). This breaks linking against static
libraries that are compiled without position independent code (PIC).

Building GMP `--with-pic` in this case seems to be the least fragile
solution.

TEST=Run `make all` and `make BUILDGCC_OPTIONS=-b build-i386` in
     util/crossgcc on Debian Stretch.

BUG=None
BRANCH=None

Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17936
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>

Change-Id: I5f3185af9c8d599379a628e18724b217b88be974
Reviewed-on: https://chromium-review.googlesource.com/425258
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:00:21 -08:00
Nicola Corna
4eeb72781d UPSTREAM: device/dram/ddr3: add FTB timings
SPD revision 1.1 introduced FTB timings, an extra set of SPD values that
specify a more precise tCKmin, tAAmin, tRCDmin, tRPmin and tRCmin.

For backwards compatibility, the MTB is usually rounded up and the FTB
part is negative. For this reason some memories were not set up optimally,
as the FTB part was ignored and the resulting timing wasn't set to the
minimum value.

The tests were performed on a Lenovo X220 with two Micron 8KTF51264HZ-1G9E
(1866 MHz): reading only the MTB part, coreboot reports a tCKmin of
1.125 ns, corresponding to a working frequency of 800 MHz; with the
additional tCKmin FTB part (-0.054 ns) the new (rounded) value is
1.070 ns, valid for a 933 MHz operation.

Tested also with Ballistix DDR3-1866 SODIMM on Lenovo T420: the memory is
now detected as DDR3-1866 instead of DDR3-1600.

Some manufacturers (like Micron) seems to expect a small rounding on the
timings, so a nearest-value rounding is performed. If this assumption
isn't correct, an error up to ~2 ps can be committed, which is low enough
to be safely ignored.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/17476
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: Ib98f2e70820f207429d04ca6421680109a81f457
Reviewed-on: https://chromium-review.googlesource.com/425257
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:00:18 -08:00
Lee Leahy
11a32401c6 UPSTREAM: console: Enable do_printk_va_list for VBOOT
Use CONFIG_VBOOT to enable do_printk_va_list to match the conditionals
in include/console/console.h and the only caller is vboot/vboot_logic.c.
CONFIG_VBOOT is also selected for CONFIG_CHROMEOS.

TEST=Build and run on Galileo Gen2

BUG=None
BRANCH=None

Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/17967
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ia115c74afa498a14d5edd6f7940ec2edc124516f
Reviewed-on: https://chromium-review.googlesource.com/425256
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:00:16 -08:00
Matt DeVillier
e28af0e812 UPSTREAM: cpu/intel/common: Add/Use common function to set virtualization
Migrate duplicated enable_vmx() method from multiple CPUs to common
folder.  Add common virtualization option for CPUs which support it.

Note that this changes the default to enable virtualization on CPUs
that support it.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17874
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)

Change-Id: Ib110bed6c9f5508e3f867dcdc6f341fc50e501d1
Reviewed-on: https://chromium-review.googlesource.com/425255
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:00:14 -08:00
Marshall Dawson
5c1ee22f8f UPSTREAM: amd-based mainboards: Fix whitespace in _PTS comments
Correct tabs that were intended as spaces.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17905
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)

Change-Id: Idcf33d829f87a866b5ed880527102918d5b93842
Reviewed-on: https://chromium-review.googlesource.com/425254
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:00:11 -08:00
Sumeet Pawnikar
b57ad453fe UPSTREAM: mainboard/google/chell: Set TCC activation offset to 10 degree C
With the default TCC activation offset value as 0 and Tjmax
temperature value as 100 degree C, Pcode firmware starts taking
prochot action at 100 degree C [Tjmax-Offset].

But before Pcode firmware starts prochot action at 100 degree C,
device is getting shutdown at 99 degree C due to DPTF critical
CPU temperature.

This patch sets TCC activation offset value to 10 degree C for
thermal throttle action to prevent this kind of shutdown.

BUG=chrome-os-partner:59397
BRANCH=None.
TEST=Built, booted on skylake and verified target offset value.

Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/17921
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I0811ef481a4b3ce4bd6ef24f2aa8160f44f9c990
Reviewed-on: https://chromium-review.googlesource.com/425253
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:00:09 -08:00
Sumeet Pawnikar
f47ba97d63 UPSTREAM: soc/intel/skylake: set TCC activation by BSP only
TCC activation functionality has package scope. It was set
for all CPU in the system which is unnecessary.
In this patch TCC activation is being set by the BSP only.

BUG=chrome-os-partner:59397
BRANCH=None.
TEST=Built for skylake platform and verified the TCC activation
value before and after S3.

Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/17889
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Iacf64cbc40871bbec3bede65f196bf292e0149a6
Reviewed-on: https://chromium-review.googlesource.com/425252
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:00:06 -08:00
Furquan Shaikh
22e7b86790 UPSTREAM: spi: Get rid of SPI_ATOMIC_SEQUENCING
SPI_ATOMIC_SEQUENCING was added to accomodate spi flash controllers with
the ability to perform tx and rx of flash command and response at the
same time. Instead of introducing this notion at SPI flash driver layer,
clean up the interface to SPI used by flash.

Flash uses a command-response kind of communication. Thus, even though
SPI is duplex, flash command needs to be sent out on SPI bus and then
flash response should be received on the bus. Some specialized x86
flash controllers are capable of handling command and response in a
single transaction.

In order to support all the varied cases:
1. Add spi_xfer_vector that takes as input a vector of SPI operations
and calls back into SPI controller driver to process these operations.
2. In order to accomodate flash command-response model, use two vectors
while calling into spi_xfer_vector -- one with dout set to
non-NULL(command) and other with din set to non-NULL(response).
3. For specialized SPI flash controllers combine two successive vectors
if the transactions look like a command-response pair.
4. Provide helper functions for common cases like supporting only 2
vectors at a time, supporting n vectors at a time, default vector
operation to cycle through all SPI op vectors one by one.

BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully

Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17681
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I4c9e78c585ad95c40c0d5af078ff8251da286236
Reviewed-on: https://chromium-review.googlesource.com/424871
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:00:04 -08:00
Furquan Shaikh
73b84f4def UPSTREAM: soc/intel/skylake: Use the new SPI driver interface
1. Define controller for fast SPI.
2. Separate out functions that are specific to SPI and flash
controller in different files.

BUG=chrome-os-partner:59832
BRANCH=None

BRANCh=None
TEST=Compiles successfully for chell and eve.

Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17933
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I2fe0ef937297297339d4ea19dc37d3061caaa80c
Reviewed-on: https://chromium-review.googlesource.com/424870
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 11:00:02 -08:00
Matt DeVillier
582aa5f05e UPSTREAM: Combine Broadwell Chromeboxes using variant board scheme
Combine existing boards google/guado, rikku, and tidus using
their common reference board google/jecht as a base.

Additional changes besides simple consolidation include:
 - simplify power LED functions
 - simplify HDA verb definitions using azelia macros
 - use common SoC functions to generate FADT table
 - correct FADT table header version
 - remove unused haswell_pci_irqs.asl
 - remove unused header includes (various)
 - set sane default fan speed (0x4d) for all variants

Variant setup modeled after google/beltino

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17913
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I77a2dffe9601734916a33fd04ead98016ad0bc4b
Reviewed-on: https://chromium-review.googlesource.com/424868
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 10:59:59 -08:00
Arthur Heymans
03a0a6f8fc UPSTREAM: mb/asus/p5gc-mx: Add mainboard
Tested to work:
* GPU (Nvidia gt210) in PCIe x16 slot;
* SATA;
* serial;
* 800MHz and 1067MHz FSB Core 2 Duo CPUs;
* ethernet;
* native VGA graphic init.

What does not work:
* resume from s3 suspend;
* superio hardware monitor (not initialised in coreboot).

Quirks:
* does not boot with just one dimm in slot B.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17558
Tested-by: build bot (Jenkins)
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>

Change-Id: Ide5494be7f2f16d6b5cfd2ccf4ec438f0587add5
Reviewed-on: https://chromium-review.googlesource.com/424867
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 10:59:57 -08:00
Marshall Dawson
6d5be53a0b UPSTREAM: agesa and binaryPI mainboards: Fix devicetree hudson comments
Make the ending comment associated with "chip ...hudson" match the
appropriate directory name.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17904
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)

Change-Id: I5e0d6d41a2e3f963760aad08ed6108acac5b66b3
Reviewed-on: https://chromium-review.googlesource.com/424866
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-05 10:59:54 -08:00
Hung-Te Lin
9f5d059d27 vboot: Clear battery cutoff flags when vbnv_cmos loads backup VBNV.
When CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH is set, vbnv_cmos will try
to load VBNV from flash if the VBNV in CMOS is invalid. This is usually
correct, except the case of battery cut-off.

CMOS will always be invalid after battery cut-off if there is no RTC
battery (or if that is dead). However, in current implementation the
backup in flash is only updated in Coreboot, while the real battery
cutoff (and the clearing of cutoff flags in VBNV) is done in payload
(Depthcharge) stage. This will create an endless reboot loop that:

 1. crossystem sets battery cutoff flag in VBNV_CMOS then reboot.
 2. Coreboot backups VBNV_CMOS to VBNV_flash.
 3. Depthcharge sees cutoff flag in VBNV_CMOS.
 4. Depthcharge clears cutoff flag in VBNV_CMOS.
 5. Depthcharge performs battery cutoff (CMOS data is lost).
 6. (Plug AC adapter) Reboot.
 7. Coreboot sees invalid VBNV_CMOS, load backup from VBNV_flash.
 8. Jump to 3.

As a result, we should always clear battery cutoff flags when loading
backups from VBNV_flash.

BRANCH=glados,reef
BUG=chrome-os-partner:61365,chrome-os-partner:59615
TEST=emerge-reef coreboot bootimage;

Change-Id: I3250a3a179a7b0de9c6e401e4a94dcd23920e473
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/423460
Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-12-30 01:41:27 -08:00
Duncan Laurie
bd3e165850 google/eve: Enable internal pull-up on PWRBTN#
Enable an internal pull-up on the power button input as a quick
press is resulting in power button override being asserted.

BUG=chrome-os-partner:61312
BRANCH=none
TEST=tested on eve P0b to ensure quick power button press does
not result in a shutdown due to power button override.

Change-Id: I0eda182b62890edfcfdeec5b24b2d418be1897de
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/424139
Commit-Ready: Duncan Laurie <dlaurie@google.com>
Tested-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
2016-12-24 19:52:32 -08:00
Brenton Dong
bf9bb94b0c UPSTREAM: soc/intel/apollolake: allow ApolloLake SoC to use FSP CAR Init
FSP v2.0 Driver supports TempRamInit & TempRamExit APIs to initialize
& tear down Cache-As-Ram.  Add TempRamInit & TempRamExit usage to
ApolloLake SoC when CONFIG_FSP_CAR is enabled.

Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram
is correctly set up and torn down using the FSP v2.0 APIs
without coreboot implementation of CAR init/teardown.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/17063
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ifd6fe8398ea147a5fb8c60076b93205bb94b1f25
Reviewed-on: https://chromium-review.googlesource.com/422956
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-21 03:13:28 -08:00
Brenton Dong
d4471b5705 UPSTREAM: drivers/intel/fsp2_0: add FSP TempRamInit & TempRamExit API support
FSP v2.0 Specification adds APIs TempRamInit & TempRamExit for
Cache-As-Ram initialization and teardown.  Add fsp2_0 driver
support for TempRamInit & TempRamExit APIs.

Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram
is correctly set up and torn down using the FSP v2.0 APIs
without coreboot implementation of CAR init/teardown.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/17062
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I482ff580e1b5251a8214fe2e3d2d38bd5f3e3ed2
Reviewed-on: https://chromium-review.googlesource.com/422955
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-21 03:13:25 -08:00
Elyes HAOUAS
ae13e6e4af UPSTREAM: nb/i945/early_init.c: Add FSB800 and 1067 to Egress Port Virtual Channel
Values based on vendor bios and suggested by Arthur Heymans for FSB1067.
FSB1067:
The ratio 1067/800 is proportional to the ratio of EPBAR32(0x2c) bits:
0x1a / 0x14 ~ 1067/800
EPVC1IST:
The ratio is also proportional to FSB ratios: 0x9c / 0xf0 ~ 533/800.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/17198
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

Change-Id: Ib90e8ea1b82f2fcc3b5c199cace32a7f0aff4b5c
Reviewed-on: https://chromium-review.googlesource.com/422954
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-21 03:13:23 -08:00
Arthur Heymans
6d3b83d40a UPSTREAM: mb/google/slippy: Hook up libgfxinit
Both HDMI and eDP work (simultaneously).

TESTED on Acer C720 (peppy).

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17916
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)

Change-Id: Ifc4e3c187bcabd8965d9586237a52b440bfa7f20
Reviewed-on: https://chromium-review.googlesource.com/422953
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-21 03:13:20 -08:00
Arthur Heymans
b5f8028a52 UPSTREAM: nb/intel/haswell: Hook up libgfxinit
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17915
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>

Change-Id: I55e2d99b3f9929703f34d268f4490f3c5c2c766f
Reviewed-on: https://chromium-review.googlesource.com/422952
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-21 03:13:18 -08:00
Paul Menzel
16bafecfaa UPSTREAM: mb/lenovo/x60: Remove PCI reset code from romstage
Commit bf264e94 (i945:) adds a PCI reset to the romstage, and commit
bc8613ec (Fix i945 based boards) fixes that to use the correct
delay of 200 ms. This code was then copied over, when adding support for
the Lenovo X60.

The reset was related to the shipped crypto card on the Roda RK886EX and
Kontron 986LCD-M, so is not needed on the Lenovo X60. So remove it.

TEST=Build and boot on Lenovo X60t.
BUG=None
BRANCH=None

Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/17703
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>

Change-Id: Ia37d9f0ecf5655531616edb20b53757d5d47b42f
Reviewed-on: https://chromium-review.googlesource.com/422951
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-21 03:13:16 -08:00
Ronald G. Minnich
0c2cba9dc0 UPSTREAM: riscv: enable counters via m[us]counteren
The user and supervisor counters could not be safely enabled
before as the register numbers were not finalized. Now that
everyone agrees, we can enable them. Until we are sure the
toolchains are caught up, we use the hardcode name with
the register names in comments. As soon as toolchains
settle down we'll do one more pass and convert to
the symbolic names.

Tested on lowrisc bitstream and SPIKE simulator.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17920
Tested-by: build bot (Jenkins)
Reviewed-by: Alex Bradbury <asb@lowrisc.org>
Reviewed-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-by: Andrew Waterman <aswaterman@gmail.com>

Change-Id: I21fe5cac44fafe4b7806e004c179aa27541be4b6
Reviewed-on: https://chromium-review.googlesource.com/422950
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-21 03:13:13 -08:00
Aaron Durbin
4ae76619d8 UPSTREAM: drivers/spi: fix flash writes at page boundaries
There was an assumption that all SPI controllers could
consume a full page of data to write. However, that
assumption doesn't hold when spi_crop_chunk() indicates
sizes smaller than page size. If the requested offset isn't
page aligned from the start then writes will fail corrupting
data since a page boundary isn't honored.

The spansion driver needed quite a bit more work to honor
the spi_crop_chunk() result. It now mimics the other
driver's code. Also, needed to add spi_crop_chunk() to
marvell/bg4cd SoC to make google/cosmos build. SPI obviously
doesn't work on that platform, but it fixes the build error.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17910
Tested-by: build bot (Jenkins)
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>

Change-Id: I93e24a5a717adcee45a017c164bd960f4592ad50
Reviewed-on: https://chromium-review.googlesource.com/422949
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-21 03:13:11 -08:00
Furquan Shaikh
d81faf493c UPSTREAM: google/poppy: Add new board
Add poppy board files using kabylake and FSP 2.0.

BUG=chrome-os-partner:60713
BRANCH=None
TEST=Compiles successfully

Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17866
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: Ic9aa5093b319690ae893a21cab98d9b843000e6c
Reviewed-on: https://chromium-review.googlesource.com/422948
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-21 03:13:09 -08:00
Marshall Dawson
592f058b1c UPSTREAM: amd/mainboard: Clean up bettong, gardenia USB todos
An incorrect board name was propagated over various generations of mainboards.
Correct the comments for these.  Addressing the todo items will come in a
later patch.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17903
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>

Change-Id: I4abd028fee5087955a7b6ba8d38f99c8207d24b4
Reviewed-on: https://chromium-review.googlesource.com/422947
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-21 03:13:06 -08:00
Marshall Dawson
f314901d6f UPSTREAM: motherboard/amd: Clean up bettong, gardenia makefiles
Declutter the conditional building of fchec.c.  Use the CONFIG
setting directly instead of ifeq ().

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17902
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>

Change-Id: I6d3721764e66e5615a639c1979d60ff1291b5d33
Reviewed-on: https://chromium-review.googlesource.com/422566
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-21 03:13:04 -08:00
Marshall Dawson
caf26d9f82 UPSTREAM: amd/gardenia: Update ACPI routing
Reduce the Bettong devices and match up the comments to the
northbridge.

Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from e7c38571be6406453640d671210b2074a91f162e)

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17849
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I53adff741f5cf2bd75c37421949bd30f214f5692
Reviewed-on: https://chromium-review.googlesource.com/422565
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-21 03:13:01 -08:00
Nico Huber
5dcfa26c6b UPSTREAM: drivers/intel/gma: Use scaling to simplify fb config
Utilize libgfxinit's support for scaling to simplify the framebuffer
configuration. In case of multiple displays of different resolutions,
we had configured one framebuffer big enough for their union, each
display only showing its respective upper left window. Instead, we use
the smallest resolution now and show the whole image on all displays.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17492
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)

Change-Id: I70a9d92f88ef891703829945264f94ac7eff09b0
Reviewed-on: https://chromium-review.googlesource.com/422564
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-21 03:12:59 -08:00
Nico Huber
da07a403db UPSTREAM: drivers/intel/gma: Add textmode support with libgfxinit
Add an alternative gfxinit implementation for textmode. The legacy VGA
plane and textmode is configured through coreboot provided functions.
libgfxinit uses this plane as alternative to the usual high resolution
plane.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17279
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

Change-Id: Iad0754c50fc6faec35f49583fe1c7cb50ac6c0c5
Reviewed-on: https://chromium-review.googlesource.com/422563
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-21 03:12:57 -08:00
Nico Huber
2cc0158728 UPSTREAM: mb/kontron/ktqm77: Enable native gfx init through libgfxinit
BUG=None
BRANCH=None
TEST=None

Change-Id: Ie16b3236e7378a2062b3081e4530d7a4791b4b66
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17074
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/422562
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-21 03:12:54 -08:00
Nico Huber
45068b6fb4 UPSTREAM: nb/intel/nehalem,sandybridge: Hook up libgfxinit
BUG=None
BRANCH=None
TEST=None

Change-Id: I4288193c022cc0963b926b4b43834c222e41bb0d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16953
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/422561
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-21 03:12:52 -08:00
Nico Huber
05217ca0be UPSTREAM: drivers/intel/gma: Hook up libgfxinit
Add `libgfxinit` as another option for native graphics initialization.
For that, the function gma_gfxinit() (see drivers/intel/gma/i915.h) has
to be called by the respective northbridge/soc code.

A mainboard port needs to select `CONFIG_MAINBOARD_HAS_LIBGFXINIT` and
implement the Ada package `GMA.Mainboard` with a single function `ports`
that returns a list of ports to be probed for displays.

v2: Update 3rdparty/libgfxinit to its latest master commit to make
    things buildable within coreboot.

v3: Another update to 3rdparty/libgfxinit. Including support to select
    the I2C port for VGA.

BUG=None
BRANCH=None
TEST=None

Change-Id: I4c7be3745f32853797d3f3689396dde07d4ca950
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16952
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/422560
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-21 03:12:49 -08:00
Nico Huber
ecc4ce723d UPSTREAM: Hook up libhwbase in ramstage
It's hidden behind a configuration option `CONFIG_RAMSTAGE_LIBHWBASE`.

This also adds some glue code to use the coreboot console for debug
output and our monotonic timer framework as timer backend.

v2: Also update 3rdparty/libhwbase to the latest master commit.

BUG=None
BRANCH=None
TEST=None

Change-Id: I8e8d50271b46aac1141f95ab55ad323ac0889a8d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16951
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/422559
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-21 03:12:47 -08:00
Duncan Laurie
f91d0fe384 UPSTREAM: google/eve: Fix configuration of some GPIOs
GPP_D12 needs an internal pull-up to get this rail working on
current boards.  GPP_D0-GPP_D3 were changed from SPI interface
and I just missed this change earlier.

BUG=chrome-os-partner:58666
TEST=test camera and touchpad on eve

Original-change-id: Idfa186f2930afbe5651f4e0fc11a19cd0dd4295f
Original-signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-reviewed-on: https://review.coreboot.org/17922
Original-tested-by: build bot (Jenkins)
Original-reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ieed4e5148ef64c0f40eb7f53b0159f6a558ac390
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/422471
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-20 21:56:21 -08:00
Piotr Król
16b684416e UPSTREAM: pcengines/apu2: add board support
Initial work based on db-ft3b-ls and code released by Eltan. Board
boots with some limitation.

Now the AGESA binary is harcoded and board specific until it's fixed
by the SoC vendor.

memtest86+ from external repo skips looking for SPD on SMBus, which when
performed cause memtest86+ to hang. Still didn't tried whole test suit.

SeaBIOS 1.9.3 have some problems with USB which lead to no booting in
some cases. Full log:
https://gist.github.com/pietrushnic/787cbf63f610ff4f6b4ac13e5c20b872

SeaBIOS from PC Engines repository (https://github.com/pcengines/seabios)
works fine. Those changes are planned for upstream.

Information about obtaining and booting Voyage Linux:
https://github.com/pcengines/apu2-documentation#building-firmware-using-apu2-image-builder

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Piotr Krl <piotr.krol@3mdeb.com>
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/14138
Tested-by: build bot (Jenkins)
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>

Change-Id: Id23e448e27f4bba47b7e9e7fa7679e2690c6e4bc
Reviewed-on: https://chromium-review.googlesource.com/422246
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-19 12:24:12 -08:00
Marshall Dawson
8a0bc65682 UPSTREAM: amd/gardenia: Add AHB bridge registers in ACPI
Add the region used by the A-Link to AHB configuration registers.

Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(squashed from 2c8dafdf44cf1a84cbc25e8aa381c04c160ee705
           and 3c755f70ffa36c0fc92a1da0e3f5f877c8dc9e8b)

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17848
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I7398452c6e70b4545e16398f3fec157f2f30293a
Reviewed-on: https://chromium-review.googlesource.com/422245
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-19 12:24:10 -08:00
Marshall Dawson
4f8b7da12d UPSTREAM: amd/gardenia: Add I2C devices to ACPI
Add the missing two I2C controllers.

Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from 0be00a96b9eb40c959a422a5ca4773d2353d244d)

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17847
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I3ea74a6c0472711102b19a7ca0209aaeeeb2d601
Reviewed-on: https://chromium-review.googlesource.com/422244
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-19 12:24:07 -08:00
Marshall Dawson
9b51ca6f68 UPSTREAM: amd/gardenia: Clean up GPIO ASL
Remove the unused Name field.  Its previous design generates an FWTS
error and a recommendation for changing it to Serialized.

Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 1d970f1aa16c647e56a08c83f5719041882a2fc0)

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17846
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I27748a4f84286e80043f516564ef64350ef3fef9
Reviewed-on: https://chromium-review.googlesource.com/422243
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-19 12:24:05 -08:00
Kyösti Mälkki
5b372b34ab UPSTREAM: ti/beaglebone: Define arch for omap-header build
Required to add rules.h as default include, otherwise we get error:

   ./src/include/rules.h:128:5: error:
      "__COREBOOT_ARM_ARCH__" is not defined [-Werror=undef]

Previously, rules.h was not included in omap-header build at all.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17746
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I75265916856f2f21f7966619ea65d63acd599e2f
Reviewed-on: https://chromium-review.googlesource.com/422242
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-19 12:24:02 -08:00
Kyösti Mälkki
a1522b60c9 UPSTREAM: AMD binaryPI: Promote rules.h to default include
Also remove config.h, kconfig.h will pull that one in.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17667
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I798b3ffcf86fca19ae4b0103bb901a69db734141
Reviewed-on: https://chromium-review.googlesource.com/422241
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-19 12:24:00 -08:00
Kyösti Mälkki
ad901b1358 UPSTREAM: intel/fsp_rangeley: Fix use of __SIMPLE_DEVICE__
Required fix to have rules.h as default include.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17747
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: I6ce2d4e13de5139a84c709b5836ecd41c0abc836
Reviewed-on: https://chromium-review.googlesource.com/422240
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-19 09:55:26 -08:00
Kyösti Mälkki
0faab9ae82 UPSTREAM: intel cache-as-ram: Move DCACHE_RAM_BASE
Having same memory region set as both WRPROT and WRBACK
using MTRRs is undefined behaviour. This could happen if
we allow DCACHE_RAM_BASE to be located within CBFS in SPI
flash memory and XIP romstage is at the same location.

As SPI master by default decodes all of top 16MiB below
4GiB, initial cache-as-ram line fills may have actually
read from SPI flash even in the case DCACHE_RAM_BASE was
below the nominal 4GiB - ROM_SIZE.

There are no reasons to have this as board-specific setting.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17806
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I2cce80731ede2e7f78197d9b0c77c7e9957a81b5
Reviewed-on: https://chromium-review.googlesource.com/422239
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-19 09:55:24 -08:00
Kyösti Mälkki
73fe6ee99d UPSTREAM: intel/i82801ix: Add HAVE_INTEL_FIRMWARE
Select this to provide menu in menuconfig to add flash
descriptor file. ME or GbE firmwares themselves are not
required, but integrated NIC MAC and SPI configuration
fields are still useful.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17805
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>

Change-Id: I14b86e2f38ec39924d2cbf0932d82f66ed356a03
Reviewed-on: https://chromium-review.googlesource.com/422238
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-19 09:55:21 -08:00