Commit graph

17636 commits

Author SHA1 Message Date
Kyösti Mälkki
d119240b1b UPSTREAM: aopen/dxplplusu: Disable HW scrubber
See initialize_ecc() for the awful hack that got us around cache-as-ram
being invalidated as we do ECC HW scrubbing. It once worked, but
compiler nowadays puts more registers on the stack.

Not much interest to try fix ECC for this particular board.

Change-Id: Ie6a09e28b0af5bbf2d68af72f5d98c03df33c402
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15014
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit b62c5e8949)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/350075
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-06-06 23:34:52 -07:00
Lee Leahy
339314d83b UPSTREAM: drivers/intel/fsp1_1: Make weak routines quiet
Now that there is a better way of finding optional routines, make the
weak routines quiet so that it may be used for the optional
implementation.

TEST=Build and run on Galileo Gen2

Change-Id: Ic58c7de216394f80aee3a78dd08bd4682783be42
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15043
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry-picked from commit e747b7473e)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/350074
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-06-06 23:34:51 -07:00
Lee Leahy
dd02f59c1c UPSTREAM: mainboard/intel/galileo: Add CREATE_BOARD_CHECKLIST
Select CREATE_BOARD_CHECKLIST to create the checklist for the Quark SOC
and Galileo board.

TEST=Build and run on Galileo Gen2.

Change-Id: Ieb3e9a5a4c149cf160e11d44a515591b57fe5c83
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15004
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 287cd7563e)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/350073
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-06-06 23:34:50 -07:00
Lee Leahy
b06b1f73a1 UPSTREAM: Add Board Checklist Support
Build the <board>_checklist.html file which contains a checklist table
for each stage of coreboot.  This processing builds a set of implemented
(done) routines which are marked green in the table.  The remaining
required routines (work-to-do) are marked red in the table and the
optional routines are marked yellow in the table.  The table heading
for each stage contains a completion percentage in terms of count of
routines (done .vs. required).

Add some Kconfig values:
*  CREATE_BOARD_CHECKLIST - When selected creates the checklist file
*  MAKE_CHECKLIST_PUBLIC - Copies the checklist file into the
   Documenation directory
*  CHECKLIST_DATA_FILE_LOCATION - Location of the checklist data files:
   *  <stage>_complete.dat - Lists all of the weak routines
   *  <stage>_optional.dat - Lists weak routines which may be optionally
      implemented

TEST=Build with Galileo Gen2.

Change-Id: Ie056f8bb6d45ff7f3bc6390b5630b5063f54c527
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15011
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit fc3741f379)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/350072
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-06-06 23:34:49 -07:00
Lee Leahy
dd865eb43d UPSTREAM: mainboard/intel/galileo: Set board version
Return the correct board version in SMBIOS.

TEST=Build and run on Galileo Gen2

Change-Id: I97ec7bcd475142eb90930152da0244a3c5d09634
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15041
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit eb0e7bc976)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/350071
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-06-06 23:34:49 -07:00
Julius Werner
ded7c748e0 UPSTREAM: chromeec: Move EC image hash to separate file in CBFS
The Chrome OS bootloader is changing its EC software sync mechanism to
look for the hash of an EC image in a separate CBFS file, rather than
using the CBFS hash attribute of the image itself (see
http://crosreview.com/348061). This patch makes coreboot generate
appropriate hash files for the new format when it builds and bundles a
Chrome EC image. This also allows us to compress the EC image itself.

Change-Id: I9aee6b8d24cdf41cb540db86a7569038fc7d9937
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/15039
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry-picked from commit 8e97d00755)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/350070
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-06-06 23:34:48 -07:00
Lin Huang
69a1133635 rockchip: gru: pass poweroff gpio parameter to BL31
To support gpio power off SOC, we need to pass the power off
gpio parameter to BL31. Gru reuse tsadc overtemp pin as power
off gpio, so need to iomux to gpio function when use gpio power
off function, either in bl31 or depthcharge.

BRANCH=None
BUG=chrome-os-partner:53448
TEST=Build gru

Change-Id: Ie7a1bbea4a12753f0abac7a9142f2e032686ce31
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349703
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-06-03 18:03:35 -07:00
Lin Huang
ad6231b121 rockchip: gru: pass reset gpio parameter to BL31
To support gpio reset SOC, we need to pass the reset gpio
parameter to BL31. Note: request BL31 have supported this
function.

BRANCH=None
BUG=chrome-os-partner:51924
TEST=Build gru

Change-Id: I8283596565d552b1f3db31c28621a1601c226999
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349702
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-06-03 18:03:34 -07:00
Lin Huang
53844cb28b rockchip: gpio: add macro so we can get gpio number
sometimes we need gpio number, so add this macro so we
can get the gpio number if we need.

BRANCH=None
BUG=chrome-os-partner:51924
TEST=Build gru

Change-Id: I98e8cf15543179904295a86e9f720c2d7c8b443a
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/349701
Commit-Ready: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-06-03 18:03:33 -07:00
Lin Huang
af83e1bafb rockchip: rk3399: pass board specific message to BL31
Sometime we need to pass board specific message to BL31,
with that BL31 can do board specific operate base on
common code.

BRANCH=None
BUG=chrome-os-partner:51924
TEST=Build gru

Change-Id: Ib7585ce7d3bf01d3ce53b388bf9bd60f3b65f5f1
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349700
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-06-03 18:03:32 -07:00
Kyösti Mälkki
121094b78f UPSTREAM: AGESA boards: Drop unused include
These files do not use definitions from OptionsIds.h. Also those
definitions are required and already included for Ids.h.

Change-Id: I149fcfe2ad72fe3d7390ee2043a86432aeae3f08
Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14980
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/349433
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-03 08:55:14 -07:00
Ben Gardner
4f739e13ce UPSTREAM: intel/fsp_baytrail/i2c: mask i2c interrupts in i2c_init()
i2c_init() leaves the I2C device enabled. Combined with the default
interrupt mask (0x8ff) and the fact that the interrupt line is shared,
this leads to an interrupt storm in the OS until a proper I2C driver
is loaded.

This change clears the interrupt mask to prevent the interrupt storm.

Change-Id: I0424a00753d06e26639750f065a7a08a710bfaba
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/15047
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/349432
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-03 08:55:13 -07:00
Furquan Shaikh
770e4b47db UPSTREAM: intel/apollolake: Clear TSEG reg early in bootblock
TSEG register comes out of reset with a non-zero default value. This
causes issues when cbmem_top returns non-zero value based on TSEG read
before DRAM is initialized. Thus, clear TSEG reg early in bootblock to
avoid unwanted side-effects.

Change-Id: Id3c6c270774108e4caf56e2a07c5072edc65bb58
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15049
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/349431
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
2016-06-03 08:55:12 -07:00
Lee Leahy
8bae1e76e0 UPSTREAM: quark: Enable HSUART0 as console
The use of HSUART0 on galileo requires early initialization of the I2C
GPIO expanders to direct the RXD and TXD signals to DIGITAL 0 and 1
on the expansion connector.

TEST=None

Change-Id: I11195d79e954c1f6bc91eafe257d7ddc1310b2e7
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15010
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit bc518d5cab)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348425
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-06-02 14:06:52 -07:00
Lee Leahy
13c8448418 UPSTREAM: soc/intel/quark: Move UART init into romstage.c
Move UART initialization into romstage.c and eliminate uart.c.

TEST=Build and run on Galileo Gen2

Change-Id: I5f2c9b4c566008000c2201c422a0bba63da64487
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15009
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit ac78db3a53)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348424
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-06-02 14:06:51 -07:00
Lee Leahy
22aa28cc8b UPSTREAM: mainboard/intel/quark: Enable reg_access during romstage
Turn on reg_access during romstage.

TEST=Build and run on Galileo Gen2

Change-Id: Iff1616836d6031f43d7741693febefa0bf26b948
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15008
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit fd91dee420)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348423
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-06-02 14:06:50 -07:00
Lee Leahy
da5017ccb6 UPSTREAM: soc/intel/quark: Split I2C out from driver
Split out the I2C code to allow I2C transactions during early romstage.

TEST=Build and run on Galileo Gen2

Change-Id: I87ceb0a8cf660e4337738b3bcde9d4fdeae0159d
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15007
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit a5258cba6f)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348422
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-06-02 14:06:49 -07:00
Lee Leahy
c2a4fe7d48 UPSTREAM: soc/intel/quark: Set temporary I2C base address
Set a temporary I2C base address during romstage.

TEST=Build and run on Galileo Gen2

Change-Id: I4b427c66a4e7e6d30cc611d4d3c40bb0ea36066d
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15006
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 56c99f2850)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348421
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-06-02 14:06:48 -07:00
Lee Leahy
c3b2f0034f UPSTREAM: mainboard/intel/galileo: Use HSUART1 for console
Select HSUART1 for console.

TEST=Build and run on Galileo Gen2

Change-Id: I4425af4dc8b3730b3fa2108d6cc2941bc22c2cdb
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15005
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit ca65bb7b4e)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348420
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-06-02 14:06:47 -07:00
Lee Leahy
356d768e0c UPSTREAM: Documentation/Intel/Board: Add analog switch link
Add link for TI TS5A23159 specification.

TEST=None

Change-Id: I2756ded963fc7597e4db1fa151bf62630b1108d9
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15003
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 2a8cc3064e)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348419
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-06-02 14:06:46 -07:00
Lee Leahy
d30a49d613 UPSTREAM: soc/intel/quark: Conditionally define BIT names
Only define BIT names if they are not already defined.

TEST=Build and run on Galileo Gen2

Change-Id: Ief4c4bb7a42a1bb2a7f46f13dc9b8bbb4d233e3c
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15002
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit d5493683ea)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348418
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-06-02 14:06:45 -07:00
Lee Leahy
14572c3a52 UPSTREAM: mainboard/intel/galileo: Split out enabling FSP1_1
Split out enabling FSP 1.1 support to prepare for enabling FSP 2.0
support.

TEST=Build and run on Galileo Gen2.

Change-Id: Ic4e814bcf61f9480f98e2d7bc7a1648dec43a07d
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15001
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 5e808cb811)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348417
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-06-02 14:06:45 -07:00
Lee Leahy
b7622710aa UPSTREAM: soc/intel/quark: Fix reg_script display
Remove extra :  following reigster type.

TEST=Build and run on Galileo Gen2

Change-Id: I57dd40a540d7b5371a6c45174f47a311b83a2aab
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14948
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 6b24dfce74)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348416
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-06-02 14:06:44 -07:00
Lee Leahy
baf25a0e50 UPSTREAM: soc/intel/quark: Clear SMI interrupts and wake events
Migrate the clearing of the SMI interrupts and wake events from FSP into
coreboot.

TEST=Build and run on Galileo Gen2

Change-Id: Ia369801da87a16bc00fb2c05475831ebe8a315f8
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14945
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 7f4b053980)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348415
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-06-02 14:06:43 -07:00
Lee Leahy
88e66bc38e UPSTREAM: soc/intel/quark: Rename pmc.c to lpc.c
Rename the file pmc.c to lpc.c to prepare for further additions.

TEST=Build and run on Galileo Gen2

Change-Id: If98825d72878f0601f77bff8c766276dbda8a9ae
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14946
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 773ee2bb17)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348414
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-06-02 14:06:42 -07:00
Lee Leahy
b78341a070 UPSTREAM: soc/intel/quark: Add PCIe reset support
Migrate PCIe reset from PlatformPciHelperLib in QuarkFspPkg into
coreboot.

Change-Id: I1c33fa16b0323091e8f9bd503bbfdb8a253a76d4
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14944
Original-Reviewed-by: Martin Roth <martinroth@google.com>
(cherry-picked from commit 5ef051a53a)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348413
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-06-02 14:06:41 -07:00
Matt DeVillier
0ca0fd893a UPSTREAM: google/ninja: Upstream AOpen Chromebox Commerical
Migrate google/ninja (AOpen Chromebox Commerical) from Chromium tree to
upstream, using google/rambi as a reference.

original source:
branch firmware-ninja-5216.383.B
commit 582a393 [Ninja, Sumo: Add SPD source for Hynix H5TC4G63CFR-PBA]

TEST=built and booted Linux on ninja with full functionality

blobs required for working image:
VGA BIOS (vgabios.bin)
firmware descriptor (ifd.bin)
Intel ME firmware (me.bin)
MRC (mrc.elf)
external reference code (refcode.elf)

Change-Id: I0f1892c24c08fa2d53185b2cf8b6f5a9001b2397
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/14950
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry-picked from commit a87fcabd2e)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348412
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-06-02 14:06:40 -07:00
Furquan Shaikh
0aeaf1575c UPSTREAM: intel/apollolake: Add car.c to verstage
Verstage on apollolake requires the functions defined in car.c to
perform flush of l1d to l2 on loading romstage into CAR.

Change-Id: I6d9a0b9dfb58c2126ad70172846e90663e588857
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15046
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349016
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
2016-06-02 14:06:39 -07:00
Furquan Shaikh
d6b5325a10 UPSTREAM: cbfs: Use NO_XIP_EARLY_STAGES to decide if stage is XIP
Modern platforms like Apollolake do not use XIP for early stages. In
such cases, cbfs_prog_stage_load should check for NO_XIP_EARLY_STAGES
instead of relying on ARCH_X86 to decide if a stage is XIP.

Change-Id: I1729ce82b5f678ce8c37256090fcf353cc22b1ec
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15045
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349015
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
2016-06-02 14:06:38 -07:00
Furquan Shaikh
eb8edcd475 UPSTREAM: google/reef: Select UART_FOR_CONSOLE for reef
Change-Id: I714af8ab552dc1923a1b64e0c502d6c7b96dd444
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15044
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349014
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
2016-06-02 14:06:38 -07:00
Iru Cai
63440d8ddc UPSTREAM: lenovo/t420: correct the eSATA port
The eSATA port of Lenovo T420 is port 3. I've checked it on an iGPU
model and a dGPU model.

Change-Id: I64bcc887140c1634dd1475d29e97780a5128d0be
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/14632
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/349013
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-02 14:06:37 -07:00
Lee Leahy
55d1adc983 UPSTREAM: drivers/intel/fsp1_1: Update weak MRC cache routines
Update the weak functions for the MRC cache.

TEST=Build and run on Galileo Gen2

Change-Id: I54a1252cfff1a2f68b163f0feb65e2bceb37f6a9
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15042
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349012
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
2016-06-02 14:06:36 -07:00
Kyösti Mälkki
9879db8607 UPSTREAM: SMBIOS: Implement SKU field
Leave it for the platform to fill in the string.

Change-Id: I7b4fe585f8d1efc8c9743f0d8b38de1f98124aab
Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14996
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
Reviewed-on: https://chromium-review.googlesource.com/349066
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
2016-06-02 14:06:35 -07:00
Duncan Laurie
ba8aa8f369 UPSTREAM: generic: Add a Maxim 98357A codec driver
The Maxim Integrated 98357A codec is an I2S slave device that has no
control channel for configuration and instead provides a GPIO that is
used for channel selection and power down.  This means it does not fit
into a bus hierarchy easily and is instead represented as a generic
device and found with a static bus scan using the devicetree.

This driver provides configuration options for passing the "sdmode" GPIO
descriptor as well as a second option for "sdmode delay" which can
configure the timing of the sdmode toggling in relation to the I2S
channel output.

In addition an GPIO can be provided to indicate to the driver whether
this device is present or not.  This can be used for board designs that
may have different codec possibilities that are selected by HW strap.

Sample usage for this device driver:

device pci 1f.3 on
  chip drivers/generic/max98357a
    register "sdmode_gpio" = "ACPI_GPIO_OUTPUT(GPP_C6)"
    register "sdmode_delay" = "100"
    device generic 0 on end
  end
end

Will result in the following code in the SSDT:

Scope (\_SB.PCI0.HDAS) {
  Device (MAXM) {
    Name (_HID, "MX98357A")
    Name (_UID, Zero)
    Name (_DDN, "Maxim Integrated 98357A Amplifier")
    Method (_STA) { Return (0xF) }
    Name (_CRS, ResourceTemplate () {
      GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly,
              "\\_SB.PCI0.GPIO", 0, ResourceConsumer)
    })
    Name (_DSD, Package () {
      ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
      Package () {
        Package () { "maxim,sdmode-gpio", \_SB.PCI0.HDAS.MAXM, 0, 0, 0 }
        Package () { "maxim,sdmode-delay", 100 }
        Package () { "sdmode-delay", 100 }
      }
    })
  }
}

Change-Id: Ia0bafe49bea9bbe4a3cc0f9f9cdb6f6390da57b5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15017
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349065
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
2016-06-02 14:06:34 -07:00
Duncan Laurie
08d309c6e0 UPSTREAM: i2c: Add a generic i2c driver
This adds a generic I2C driver that can be described in the devicetree
and used to generate ACPI objects in the SSDT based on the information
provided in the config registers.

The I2C bus can be configured and the device can provide an interrupt and
wake capability to the OS.  A configuration option allows for a GPIO to
be provided that will be checked to determine if the device is preset on
the board before including it in the generated SSDT.

The driver is generic enough to be used for basic I2C devices that do
not have special configuration needs such as touchpads, touchscreens,
sensors, some audio codec/amplifiers, etc.

Sample usage for a touchpad device:

device pci 15.1 on
  chip drivers/i2c/generic
    register "hid" = ""ELAN0000""
    register "desc" = "ELAN Touchpad"
    register "irq" = "IRQ_EDGE_LOW(GPP_B3_IRQ)"
    register "wake" = "GPE0_DW0_05"
    device i2c 15.0 on end
  end
end

Will result in the following code in the SSDT:

Scope (\_SB.PCI0.I2C1) {
  Device (D015) {
    Name (_HID, "ELAN0000")
    Name (_UID, 0)
    Name (_S0W, 4)
    Name (_PRW, Package () { 5, 3 })
    Method (_STA) { Return (0x0f) }
    Name (_CRS, ResourceTemplate () {
      I2cSerialBus (0x15, ControllerInitiated, 400000, AddressingMode7Bit,
                    "\\_S.PCI0.I2C1", 0, ResourceConsumer)
      Interrupt (ResourceConsumer, Edge, ActiveLow) { 51 }
    })
  }
}

Change-Id: Ib32055720835b70e91ede5e4028ecd91894d70d5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15016
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349064
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
2016-06-02 14:06:33 -07:00
Duncan Laurie
2a97b4b4ab UPSTREAM: drivers/intel/wifi: Add support for generating SSDT table
Intel WiFi devices that support wake-on-wifi need to declare a Power
Resource for this wake pin.  Typically this has been done with a
static declaration in the DSDT for each mainboard.  By adding it to
the existing intel/wifi driver it can be done based on a
configuration register in the devicetree.

Additionally the WiFi regulatory domain can be set in the SSDT
directly instead of needing to use NVS to pass the value to the DSDT.

Also add device IDs for Wilkins Peak 2 and Stone Peak 2 devices that
are found on Chromebooks, and clean up a long line and some comment
formatting.

This was tested by booting on an HP Chromebook 13 device and comparing
that the output in the SSDT matches what used to be in the DSDT.  The
WRDD value is read from VPD, if present, not from devicetree.cb.

Additionally the case where CONFIG_DRIVERS_INTEL_WIFI is enabled but
the wifi device is not described in devicetree.cb is tested to ensure
it still generates the AML but does not include the _PRW wake pin.

Example:

devicetree.cb:
  device pci 1c.0 on
    chip drivers/intel/wifi
      register "wake" = "GPE0_DW0_16"
      device pci 00.0 on end
    end
  end

VPD:
  "region"="us"

SSDT.dsl:
  Scope (\_SB.PCI0.RP01) {
    Device (WIFI) {
      Name (_UID, Zero)
      Name (_DDN, "Intel WiFi")
      Name (_ADR, 0x00000000)
      Name (_PRW, Package () { 16, 3 })
      Name (WRDD, Package () {
        Zero,
        Package () {
          0x00000007,
          0x00004150
        }
      })
    }
  }

Change-Id: I8b5c916f1a04742507dc1ecc9a20c19d3822b18c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15019
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349063
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
2016-06-02 14:06:32 -07:00
Duncan Laurie
6c5448125c UPSTREAM: wrdd: Export WRDD info in the header
Export the WRDD spec revision and WiFi domain type in the header
file so it can be used to generate ACPI tables by wifi drivers.

Change-Id: I3222eca723c52fe74a004aa7bac7167264249fd1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15018
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349062
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
2016-06-02 14:06:32 -07:00
Lee Leahy
22077e4f57 UPSTREAM: Documentation/Intel/Board: Add Galileo checklist
Add the Galileo implementation checklist.

TEST=None

Change-Id: I47e87a496cf3ae125d45c09fe6a36200f5fe724f
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15012
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/349061
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-02 14:06:31 -07:00
Patrick Rudolph
b1f3095809 UPSTREAM: mb/lenovo/T4xx: enable PEG device
Enable the PEG device in devicetree to expose the
device if any. This is already default behaviour
for T5xx series.

Change-Id: I16bd253ca96c4cdaad8a829f6490cec9e2599b5f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/14448
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
Reviewed-on: https://chromium-review.googlesource.com/349060
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-02 14:06:30 -07:00
Patrick Rudolph
f0b2b58584 UPSTREAM: drivers/lenovo: Add hybrid graphics driver
Add a universal hybrid graphics driver compatible with
all supported lenovo devices.
Hybrid graphics allows to connect the display panel to
either of one GPUs.
As there are only two GPUs one GPIO needs to be toggled.
In case the discrete GPU is activated the panel is routed to it.
On deactivation the panel is routed to the integrated
GPU.
On lenovo laptops the dGPU is always connected to PEG10 and it is
save to disable the PEG slot on dGPU deactivation.

Use common gpio.c for southbridge I82801IX.

Tested on Lenovo T520 using Nvidia NVS 5200m.

Removed Lenovo T430s from the list of supported devices,
as the T430s only supports "muxless Optimus".

Depends on change id:
Iccc6d254bafb927b6470704cec7c9dd7528e2c68
Ibb54c03fd83a529d1ceccfb2c33190e7d42224d8
I8bd981c4696c174152cf41caefa6c083650d283a
Iaf0c2f941f2625a5547f9cba79da1b173da6f295
I994114734fa931926c34ed04305cddfbeb429b62

Change-Id: I9b80b31a7749bdf893ed3b772a6505c9f29a56d1
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/12896
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
Reviewed-on: https://chromium-review.googlesource.com/349059
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-02 14:06:29 -07:00
Patrick Rudolph
676c796795 UPSTREAM: Revert "mainboard/lenovo/t400: Add initial hybrid graphics support"
This reverts commit 59597ead1f.
Will be replaced by lenovo common hybrid driver.

Change-Id: I994114734fa931926c34ed04305cddfbeb429b62
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/12895
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
Reviewed-on: https://chromium-review.googlesource.com/349058
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-02 14:06:28 -07:00
Duncan Laurie
5944b7e665 UPSTREAM: nau8825: Add driver for I2C codec
The Nuvoton NAU8825 audio codec is an I2C device that has a number of
tunable parameters that can be provided to the kernel device driver for
basic configuration and optimal operation.

The configuration options are exposed to devicetree as registers and then
presented as Device Properties via ACPI to the operation system.

This sample configuration in devicetree:

device pci 19.2 on
  chip drivers/i2c/nau8825
    register "irq" = "IRQ_LEVEL_LOW(GPP_F10_IRQ)"
    register "jkdet_enable" = "1"
    register "sar_threshold_num" = "2"
    register "sar_threshold[0]" = "0x0c"
    register "sar_threshold[1]" = "0x1c"
    device i2c 1a on end
  end
end

Will generate the following code in the SSDT, trimmed for this commit
message as there are more properties that can be configured:

Scope (\_SB.PCI0.I2C4)
{
  Name (_HID, "10508825")
  Name (_UID, Zero)
  Name (_DDN, "Nuvoton NAU8825 Codec")
  Method (_STA) { Return (0xF) }
  Name (_CRS, ResourceTemplate () {
    I2cSerialBus (0x1A, ControllerInitiated, 0x61A80, AddressingMode7Bit,
                  "\_SB.PCI0.I2C4", 0, ResourceConsumer)
    Interrupt (ResourceConsumer, Level, ActiveLow) { 0x3A }
  })
  Name (_DSD, Package () {
    ToUUID ("daffd814-6eba-4d8c-8a91-bc9bff4aa301"),
    Package () {
      Package () { "nuvoton,jkdet-enable", 1 },
      Package () { "nuvoton,sar-threshold-num", 2 },
      Package () { "nuvoton,sar-threshold", Package () { 0x0c, 0x1c } }
    }
  })
}

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I480d72daf5ac3dded9b1cbb5fbc737b9dfde3834
Reviewed-on: https://review.coreboot.org/15015
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349057
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
2016-06-02 14:06:27 -07:00
Hannah Williams
e9cc6a6814 UPSTREAM: intel/fsp2.0: Add END_OF_FIRMWARE in enum fsp_notify_phase
Change-Id: Ib39e828c6e3145957ecc2dacc1f72de793165514
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/15020
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349056
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
2016-06-02 14:06:26 -07:00
Hannah Williams
c3d19be3e6 UPSTREAM: soc/apollolake: remove _RMV and _DSW methods from xhci.asl
Change-Id: Ic314656f34fda10e58e55bdefeb0a1f0c6ab5ae2
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/14966
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349055
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-02 14:06:26 -07:00
Shaunak Saha
867d26ef18 UPSTREAM: intel/apollolake: Add support to enable google ChromeEC
ChromeEC is needed for EC controlled features to work properly.
This patch adds neccessary support in soc/intel so that mainboard
asl files can include the ChromeEC e.g. PNOT method and
LPCB and also the nvs fields.

BUG = 53096
TEST = This patch is needed by the mainboard specific ASL change to include
       src/ec/google/chromeec/acpi/ec.asl

Change-Id: Icecc437df05cd3efb41579317a353fd22526e0c9
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/14967
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349054
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
2016-06-02 14:06:25 -07:00
Furquan Shaikh
28ef81d4b8 UPSTREAM: soc/intel/apollolake: add support for IFWI region
On apollolake, the boot media layout is different in that the traditional
"BIOS" region contains another data structure with the boot assets such
as CSE firmware, PMC microcode, CPU microcode, and boot firmware to name
a few. This region is referred to as the IFWI. Add support for writing
the IFWI to a specified FMAP region to accommodate such platforms.

Change-Id: Ia61f12a77893c3dd3256a9bd4e0f5eca0065de26
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14999
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349053
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
2016-06-02 14:06:24 -07:00
Furquan Shaikh
d38af3c2a7 UPSTREAM: Makefile: Add ifwitool to list of tools to be built
Add ifwitool to list of tools to be built so that it can be used by the
build system.

Change-Id: Ifcfbfd87ad9b7ba3ea11cfbcf40894f3e0dae694
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15013
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349052
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
2016-06-02 11:09:13 -07:00
Furquan Shaikh
9037ff4585 UPSTREAM: ifwitool: Fix syntax issues with ifwitool
CQ-DEPEND=CL:348067
BUG=chrome-os-partner:53689
BRANCH=None
TEST=Compiles successfully

Change-Id: Ie7a12a39116ee08f5e24c81c97695201169a63f7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15022
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349051
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
2016-06-02 11:09:12 -07:00
Furquan Shaikh
1fe61451c1 UPSTREAM: ifwitool: Add new tool for managing IFWI images
- Supports following operations:
 1. add raw/dir sub-partition
 2. extract raw/dir sub-partition
 3. print info
 4. delete raw sub-partition
 5. replace raw/dir sub-partition

CQ-DEPEND=CL:349051
BUG=chrome-os-partner:53689
BRANCH=None
TEST=Compiles successfully

Change-Id: I88c9a13d8cce0b845fbd572593991fe99e64df08
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14896
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348067
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
2016-06-02 11:09:11 -07:00
Furquan Shaikh
cd42413afe UPSTREAM: mainboard/google/reef: Add IFWI region to chromeos.fmd
IFWI region holds different components required for booting including
CSE firmware, PMC firmware, CPU microcode as well as the bootblock. Add
section for IFWI in chromeos.fmd

Change-Id: Ic97980ff222ad7cbd7a2970417b79150256a7a16
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15000
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349050
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
2016-06-02 11:09:10 -07:00