- Check out the specific toolchain version we want before building
the toolchain (This version uses 1.42).
- Add additional libraries and tools needed to build coreboot related
packages.
- Move everything required to build any of the coreboot or related
packages into the coreboot-sdk from coreboot-jenkins-node Dockerfile.
- Separate the text of the commands in the Dockerfiles.
- Use nproc to get the number of processors for building the toolchain
- Add some additional comments about why things are done the way that
they are to the README
- Update the version of coreboot-sdk that coreboot-jenkins-node uses to
1.42. (This matches the toolchain version)
- Move ccache setup from jenkins-node to coreboot-sdk.
- Update the maintainer.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16239
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: I293285ef72e3e70259355d924d425fea98ee773d
Reviewed-on: https://chromium-review.googlesource.com/373023
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the coreboot specific docker configuration files to the coreboot
repo. These have been copied directly from Patrick's repo where they
had been being stored.
- coreboot-sdk: debian sid with the coreboot toolchain
- coreboot-jenkins-node: built on top of the coreboot-sdk, adds the
pieces required for building everything with the coreboot jenkins
builders.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14830
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: I8628d4edb298264e814e02e124a8bfb4bc04e0c7
Reviewed-on: https://chromium-review.googlesource.com/373022
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
pmc_gpe_route_to_gpio returns -1 on error. However, the value was being
stored in unsigned int and compared against -1. Fix this by using local
variable ret.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16218
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I5ec824949d4ee0fbdbb2ffdc9fc9d4762455b27b
Reviewed-on: https://chromium-review.googlesource.com/373021
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Program MCHBAR, DMIBAR, EPBAR, EDRAMBAR and GDXCBAR.
Also program the PAM registers. The system agent was being
programmed in romstage during pre-console initialization, after
moving to C_ENVIRONMENT bootblock this was missing, restoring
the same.
TEST=Build and Boot Kunimitsu
BUG=None
BRANCH=None
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16224
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: Iaf310cfb83e58eb8d5affb481dfc343f5d45961b
Reviewed-on: https://chromium-review.googlesource.com/373020
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch sets some magic number in magic undocumented registers that
are rumored to make USB 2.0 signal integrity better on Kevin. I don't
see any difference (unfortunately it doesn't solve the problems with
long cables on my board), but I guess it doesn't hurt either way.
BRANCH=None
BUG=chrome-os-partner:56108,chrome-os-partner:54788
TEST=Booted Kevin with USB connected through Servo. Seems to have
roughly the same failure rate as before.
Change-Id: Ifbd47bf6adb63a2ca5371c0b05c5ec27a0fe3195
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/370900
Reviewed-by: Guenter Roeck <groeck@chromium.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
In newer toolchain with binutils 2.26 and GCC 5.3.0, we build binutils
and GCC with machine type riscv32 and riscv64 instead of riscv. We can
see it in this riscv-gnu-toolchain commit:
https://github.com/riscv/riscv-gnu-toolchain/commit/dedbf07
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Signed-off-by: Martin Roth <martinroth@google.com>
BUG=None
BRANCH=None
TEST=None
Reviewed-on: https://review.coreboot.org/14257
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: Id552859ec256d80108e073d25cd51dd1fc3fbfac
Reviewed-on: https://chromium-review.googlesource.com/371505
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Martin Roth <martinroth@chromium.org>
Since commit 3bfd7cc (drivers/pc80: Rework normal / fallback selector
code) the reboot counter stored in `reboot_bits` isn't reset on a reboot
with `boot_option = 1` any more. Hence, with SKIP_MAX_REBOOT_CNT_CLEAR
enabled, later stages (e.g. payload, OS) have to clear the counter too,
when they want to switch to normal boot. So change the bits to (h)ex
instead of (r)eserved.
To clarify their meaning, rename `reboot_bits` to `reboot_counter`. Also
remove all occurences of the obsolete `last_boot` bit that have sneaked
in again since 24391321 (mainboard: Remove last_boot NVRAM option).
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/16157
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: Ib3fc38115ce951b75374e0d1347798b23db7243c
Reviewed-on: https://chromium-review.googlesource.com/371504
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Martin Roth <martinroth@chromium.org>
CONFIG_VBOOT was recently moved to be independent from CONFIG_CHROMEOS.
Change the code guard for do_printk_va_list() accordingly, since it's
used by vboot (not Chrome OS) code.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16230
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Change-Id: I44e868d2fd8e1368eeda2f10a35d0a2bd7259759
Reviewed-on: https://chromium-review.googlesource.com/371503
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Martin Roth <martinroth@chromium.org>
CONFIG_VBOOT was recently moved to be independent from CONFIG_CHROMEOS.
However, the latter still has some 'select' clauses to ensure that
required TPM libraries are built. The TPM is an essential part of vboot,
and without these libraries the vboot code cannot compile... therefore,
they should be moved under CONFIG_VBOOT.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16229
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I0145558e5127c65c6a82d62f25b5a39e24cb8726
Reviewed-on: https://chromium-review.googlesource.com/371502
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Martin Roth <martinroth@chromium.org>
Gale EVT3 has only one LED controller (earlier we had 2).
Removing the support for the second controller and also the
corresponding microcode. The color values used are the same
as onHub (Arkham to be specific).
BUG=b:30890905
TEST=Move the device to different states manually by appropriate
actions (like dev mode, rec mode etc) and observe the differnet
colors.
BRANCH=None
Change-Id: If8f22abd605faac6f6215ef600041740ce15ea0c
Signed-off-by: Suresh Rajashekara <sureshraj@google.com>
Reviewed-on: https://chromium-review.googlesource.com/370821
Commit-Ready: Suresh Rajashekara <sureshraj@chromium.org>
Tested-by: Suresh Rajashekara <sureshraj@chromium.org>
Reviewed-by: Kan Yan <kyan@google.com>
We should be running faster. Faster = better.
BRANCH=None
BUG=chrome-os-partner:54873
TEST=Boot; stressapptest -M 1028 -s 10000
Change-Id: Iec9343763c1a5a5344959b6e8c4dee8079cf8a20
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/362822
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This is a temporary work-around since the current threshold of 70 on
TSR2 results in thermal trip and shutdown while the kernel is
booting. Changing this threshold to 100 allows kernel to boot up to
userspace. Following values were read:
$ cat /sys/class/thermal/thermal_zone4/temp
81800
$ cat /sys/class/thermal/thermal_zone4/type
TSR2
BUG=chrome-os-partner:56155
BRANCH=None
TEST=Boots to OS.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16156
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I951553ed4c93b02239a51a0d3036e4a750eea04b
Reviewed-on: https://chromium-review.googlesource.com/370960
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
All flash drivers are automatically included in the build unless
COMMON_CBFS_SPI_WRAPPER was selected. However, there are cases
where these drivers are unnecessary such as certain intel platforms
where spi controller uses hardware sequencing without any ability
to manually probe the device. Therefore, provide an option that the
SoC can set the default value for. The COMMON_CBFS_SPI_WRAPPER
option is still honored by not including all drivers when that
is selected.
BUG=chrome-os-partner:56151
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16187
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: Ie9aa447da450f7c8717545f05cff800139a9e2dd
Reviewed-on: https://chromium-review.googlesource.com/370713
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This option is no longer used in the code base. Remove it.
BUG=chrome-os-partner:56151
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16186
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ia73cce7546c9839518c9e931b03c50856abc2018
Reviewed-on: https://chromium-review.googlesource.com/370712
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Make the indication of the boot device being memory mapped
separate from SPI. However, retain the same defaults that
previously existed.
CQ-DEPEND=CL:370717
BUG=chrome-os-partner:56151
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16193
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: Ibdd7c8754f9bf560a878136b1f55238e2c2549d3
Reviewed-on: https://chromium-review.googlesource.com/370711
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The BOOT_MEDIA_SPI_CHIP_SELECT option is not used in any of the
code. Remove its usage.
BUG=chrome-os-partner:56151
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16185
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I522b62a2371b8a167ce17c48117669390cda14cd
Reviewed-on: https://chromium-review.googlesource.com/370710
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Having an assignment in assert does not make sense. This seems like it
was intended to check if chip is always same as segments->chip.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16219
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
Change-Id: I297d9e76a0404a1f510d43f8b9c39e96b557689f
Reviewed-on: https://chromium-review.googlesource.com/370709
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Provide more informative messages when CONFIG_ELOG_DEBUG is enabled
as well as more informative error messages in the case of
elog_scan_flash() failing. In the sync path the in-memory buffer is
dumped in before the contents are read back from the non-volatile
backing store and dumped again if the subsequent parsing fails.
BUG=chrome-os-partner:55932
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16184
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: I716adfb246ef6fbefc0de89cd94b3c1310468896
Reviewed-on: https://chromium-review.googlesource.com/370704
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
> Overrunning array "am335x_gpio_banks" of 4 4-byte elements at element
> index 4 (byte offset 16) using index "bank" (which evaluates to 4).
As the first index is 0, also error out if the index is equal the array
size.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/16165
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: I6b6b6e010348a58931bd546dfc54f08460e8dbbc
Reviewed-on: https://chromium-review.googlesource.com/370702
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Previously, make could be built as one of the crosgcc* targets, but
there was no way to just rebuild make, as there is for IASL.
- Add an independent target - gnumake.
- Add gnumake to the help text.
- Add gnumake to the list of NOCOMPILE targets (Not compiling coreboot)
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16163
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I4df25f2e209ca14944d491dbfb8e9b085ff7aca3
Reviewed-on: https://chromium-review.googlesource.com/370699
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is a python script that does basically the same thing as the
rebase.sh script, but in the other direction. rebase.sh takes files
from the chromium tree (cros) and pulls them to the coreboot.org tree.
cborg2cros, as the name implies, updates patches to go into the cros
tree from coreboot.
It adds the 'UPSTREAM: ' identifier to the start of the commit message,
and uses the text '(cherry-picked from commit #####)' instead of
'Original-Commit-Id: #####'
It also adds the 'TEST=', 'BRANCH=', and 'BUG=' lines if they aren't
there.
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15323
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: Ibad9a5f0d0d2c713cf08e103c463e2e82768c436
Reviewed-on: https://chromium-review.googlesource.com/370698
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
3 out of 4 architectures currently zero out the payload BSS in early
assembly code, which is pointless since the code loading the payload has
already done that (with a more efficient memset). ARM64 has never had
any code like this and can run just fine without it. This also defeats
the new optimization of moving the heap out of the BSS, since all three
implementations assume that everything between _edata and _end is BSS.
We should just take this out.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16091
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I45cd2dabd94da43ff0f77e990f11c877cee6cda1
Reviewed-on: https://chromium-review.googlesource.com/370697
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
cbfs_get_handle() allocates memory for a handle and doesn't free it if
it errors out later, leaving the memory permanently leaked. Fix.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16207
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: Ide198105ce3ad6237672ff152b4490c768909564
Reviewed-on: https://chromium-review.googlesource.com/369153
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
FSP unconditionally locks parts of the NVRAM in the RTC.
This change will enable coreboot to update the locking policy
and be able to unlock the region
BUG=chrome-os-partner:55944
BRANCH=None
TEST=Check 'crossystem dev_boot_usb=1'
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/16144
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Change-Id: I70fd2bafa6ff9eb9cdf284b9780e4b90dee0f4ce
Reviewed-on: https://chromium-review.googlesource.com/369150
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In particular:
- Fix the condition of the loop that fills the mid-level page table
- Adhere to the format of sptbr
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16120
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Change-Id: I575093445edfdf5a8f54b0f8622ff0e89f77ccec
Reviewed-on: https://chromium-review.googlesource.com/369148
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
I copied it from commit e10d2def7d of spike and made sure the copyright
header is still there.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15832
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: Ie8b56cd2f4855b97d36a112a195866f4ff0feec5
Reviewed-on: https://chromium-review.googlesource.com/369147
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add GPIOs initialisation before dock check.
Needed in order to properly detect the presence or absence of the lenovo
dock.
Previously the check always reported the dock as connected and currently
it always reports it as disconnected since the GPIOs are not properly
initialised during the check.
Tested and confirmed working.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16139
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Change-Id: I7fbf8c2262a1eb5dee9cbe5e23bf44f7f8181009
Reviewed-on: https://chromium-review.googlesource.com/369145
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It was a band-aid that isn't required any more.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/16142
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ib1793ae8fe25eecf9bd5ab8e5feef0d9380b43c2
Reviewed-on: https://chromium-review.googlesource.com/369142
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
To override fallback/foo's position or alignment in region BAR, use
fallback/foo-BAR-{position,align} = 0x1234
Like for the global settings, specifying both isn't allowed
because that's rather pointless.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/16140
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I94f41ebc9f35108267265df4164f23b70e3d0bf6
Reviewed-on: https://chromium-review.googlesource.com/369140
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
They're now sorted later in the process after the per-region file lists
are determined.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/16138
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I0bba381d09dc4b99e2fe5cae16ff7ffcb5b3aa82
Reviewed-on: https://chromium-review.googlesource.com/369099
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Make sure that files with a fixed position are placed first (whose order
doesn't matter: either they collide or they don't), then all aligned
files (where we just hope that the right thing happens) and finally the
files with no further requirements (again, hope).
It's still a pretty good heuristic given a typical coreboot image.
The global sorting that happens earlier in the build flow will be
removed in the future to make room for per-region requirements.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/16137
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I269c00b2ece262c95d310b76a6651c9574badb58
Reviewed-on: https://chromium-review.googlesource.com/369098
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
