discussion. There was obviously an earlier version by Eric which I have
not looked at before writing thios one. See rev 2131 in v2.
Trivial, thus self-acked.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@140 f3766cd6-281f-0410-b1cd-43a5c92072e9
renamed the phase3 etc. to stuff like phase3_scan, so you can get a
rought idea what it is. The names mean more.
adding pci_device and, at the same time, showing how we can get rid of
the really ugly stuff that crept in. note you can specify ops in the
dts, which avoids the need for hideous stuff like this:
static void enable_dev(struct device *dev)
{
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
dev->ops = &pci_domain_ops;
pci_set_method(dev);
}
else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
dev->ops = &cpu_bus_ops;
}
}
So that foolishness is gone.
added delay functions.
Note that we have include/lib.h, and define all the functions in there,
instead of in lots of fiddly includes.
Brought back the enable op, once I understood it; renamed it to
something that makes sense.
I'll be on a plane soon, will continue to work, but at least you can see
what's going on here.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@139 f3766cd6-281f-0410-b1cd-43a5c92072e9
because not all emulators get the ram size registers right, or so we
hear.
This northbridge is still incomplete. We are not just copying the v2
one, as we are trying to undo the various hacks that crept in over the
years, due to limitations in the v2 device model. Just look at the
i440bx in v2 and you can see what I mean. We are working to find a
better way to get the job done than those hacks. They are just too
confusing for people to follow.
add an include for the northbridge makefile into the qemu Makefile.
Re-order the includes in arch/x86/Makefile so we can pick up .o files
from other places. Add a STAGE2_CHIPSET_OBJ for objects defined in those
makefiles included in mainboard.
Current issues: the enable_dev function for the i440bx is not getting
called. Enable_dev should be renamed to phase3_setup or something that
actually means something. The name as it is is totally useless.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@138 f3766cd6-281f-0410-b1cd-43a5c92072e9
start documenting the device model -- since it is clear to me from
reading v2 that not even the v2 guys totally got it
call write_tables in stage2
fix the makefile to put stage2.o first to make sure it gets
called.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@135 f3766cd6-281f-0410-b1cd-43a5c92072e9
I was meaning to check in more, but I lost 4h of work due to some ext3
problem. Bummer I believed those saying its more stable than reiserfs.
Signed-off-by: Stefan Reinauer <stepan@openbios.org>
Acked-by: Stefan Reinauer <stepan@openbios.org>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@134 f3766cd6-281f-0410-b1cd-43a5c92072e9
Remaining to be done:
PIRQ table
MP table
ACPI table
relocate the GDT reload to a sensible place -- or figure out if we even
need to bother; we're back to execute in place and the GDT is in flash
rom ==> we can leave it until we boot the payload I think.
At this point, however, we've got the basic bits to sensibly create
tables.
This has been tested and works on bochs.
It is working to a point, but still failing on qemu for reasons we don't
quite understand.
Elfboot
Found ELF candidate at offset 0
New segment addr 0x100000 size 0x21310 offset 0xc0 filesize 0x7348
(cleaned up) New segment addr 0x100000 size 0x7348 offset 0xc0
set 00100000 to 0 for 0 bytes
Copy to 00100000 from fffc3f24 for 29512 bytes
New segment addr 0x121320 size 0x48 offset 0x7420 filesize 0x48
(cleaned up) New segment addr 0x121320 size 0x48 offset 0x7420
set 00121320 to 0 for 0 bytes
Copy to 00121320 from fffcb284 for 72 bytes
Dropping non PT_LOAD segment
Dropping non PT_LOAD segment
Jumping to boot code at 0x1047c0
FILO version 0.5 (rminnich@q.ccstar.lanl.gov) Sun Feb 25 10:19:16 MST
2007
collect_sys_info: boot eax = 0xfe
collect_sys_info: boot ebx = 0xffffd4ca
collect_sys_info: boot arg = 0x1047c0
collect_linuxbios_info: NOT Searching for LinuxBIOS tables...
Can't get memory map from firmware. Using hardcoded default.
collect_sys_info: 0000000000000000-00000000000a0000
collect_sys_info: 0000000000100000-0000000002000000
collect_sys_info: RAM 32 MB
relocate: Current location: 0x1000c7-0x12142e
relocate: Relocating to 0x1fdec90-0x1fffff7... ok
Press <Enter> for default boot, or <Esc> for boot prompt...
boot: hdc1:/phase1 root=/dev/hdc1 console=ttyS0,115200
malloc_check: invalid head->prev_size: 0x0
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@133 f3766cd6-281f-0410-b1cd-43a5c92072e9
resource .c functions -- sigh -- this will be next.
fix types, fix some usage, but we do not yet generate pirqi, mptables,
or acpi. This will be next.
This code will be called from phase6 in stage 2, and probably
attached to a cpu. Or, it will be inline in the stage2.c code, since
the need for tables is generic.
I'm also going to move the cryptic usage of lgdt from here to stage 2,
phase 2, of the cpu code. The device model improvements are making it
easier to think about when things happen, we are finding.
I'm going to get lunch and go see some of brussels. It's a miserable day
but ...
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@130 f3766cd6-281f-0410-b1cd-43a5c92072e9
commit. adding support for tables.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@129 f3766cd6-281f-0410-b1cd-43a5c92072e9
We have merged the plethora of include files into one. A given linuxbios
target architecture must support all the functions described therein.
All the structs etc. in include/tables.h are known to be
architecture-independent.
We hope this new layout is easier to folow than the old one.
Todo: Remove the LGDT code from tables writing (how did THAT get in
there ;-) and put it somewhere sane; add OFW table support. We are going
to need some nice OFW table code.
Also, the license headers should be correct in this commit.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@128 f3766cd6-281f-0410-b1cd-43a5c92072e9
warnings for developing/debugging, but not for the default LinuxBIOS build.
These are purely cosmetic changes, no build process changes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@126 f3766cd6-281f-0410-b1cd-43a5c92072e9
minute.
This code has been tested; we are booting filo from flash in qemu at
this point.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@114 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@111 f3766cd6-281f-0410-b1cd-43a5c92072e9
Press <Enter> for default boot, or <Esc> for boot prompt... timed out
boot: hdc1:/phase1 root=/dev/hdc1 console=ttyS0,115200
malloc_diag: alloc: 112 bytes (3 blocks), free: 16264 bytes (1 blocks)
malloc_diag: alloc: 128 bytes (4 blocks), free: 16248 bytes (1 blocks)
file_open: dev=hdc1, path=/phase1
find_ide_controller: PCI IDE #0 not found
IDE channel 1 not found
devopen: failed to open ide
malloc_diag: alloc: 112 bytes (3 blocks), free: 16264 bytes (1 blocks)
malloc_diag: alloc: 48 bytes (2 blocks), free: 16328 bytes (1 blocks)
boot: hdc1:/phase1 root=/dev/hdc1 console=ttyS0,115200
So we've just booted our first payload in V3!
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@110 f3766cd6-281f-0410-b1cd-43a5c92072e9
FLASH. It is far simpler than before.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@109 f3766cd6-281f-0410-b1cd-43a5c92072e9
of FLASH. Since it runs out of FLASH, we have removed the need for
bounce buffer support. that in turn rips out all kinds of stuff, so it
is now simpler. We're ripping out all the checksum stuff -- lar does
that.
lar.c has some debug prints removed.
elfboot.c has some mods, but elfboot.c is going away.
cachemain.c has a few mods for using newelfboot.
Makefile reflects these changes.
Not tested, I'm going to bed though, so here you are.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@108 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@107 f3766cd6-281f-0410-b1cd-43a5c92072e9
other stages, give it 16k instead of 8
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@106 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@105 f3766cd6-281f-0410-b1cd-43a5c92072e9
* add license header to console/vtxprintf.c and arch/x86/serial.c
* clean out dead code from console/vtxprintf.c
* adapt arch/x86/serial.c to CONFIG_ stuff
* actually include config.h in CFLAGS
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@104 f3766cd6-281f-0410-b1cd-43a5c92072e9
Oddly, this error just appeared, due to clashing commits.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@103 f3766cd6-281f-0410-b1cd-43a5c92072e9
We're trying to avoid the bounce buffer mess, which is really complex,
by running elfboot out of the boot block. This code includes a really
dumb allocator in elfboot which may or may not work. It basically
allocates off the elfboot() stack.
This builds, but elfboot is not tested. That's next.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@102 f3766cd6-281f-0410-b1cd-43a5c92072e9
call it something more useful than boot.c
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@100 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@99 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@97 f3766cd6-281f-0410-b1cd-43a5c92072e9
Some updates to the docs, but these will change more.
add memcmp. Crude implementation, but it really does not matter.
add compute_ip_checksum.c
mods to elfboot. Thanks to our new design, BOUNCE BUFFERS ARE DEAD. Yee
ha!
updates to makefile
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@96 f3766cd6-281f-0410-b1cd-43a5c92072e9
* remove some warnings
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@95 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@94 f3766cd6-281f-0410-b1cd-43a5c92072e9
* add generic lib.h header for lib/ prototypes
* fix some prototypes
* put back return value parsing of stage2
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@91 f3766cd6-281f-0410-b1cd-43a5c92072e9
Fix up dts to set up ops struct member. Fix dts for qemu mainboard.
We are getting past stage2 now, it is time for elfboot.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@88 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@86 f3766cd6-281f-0410-b1cd-43a5c92072e9
Phase 1: done
Phase 2: early setup ...
Phase 2: done
Phase 3: Enumerating buses...
dev_root missing 'ops' initialization
Allocating resources...
dev_root missing ops initialization
Enabling resources...
done.
Phase 6: Initializing devices...
Phase 6:Devices initialized
Now to fix up the device stuff. Once this is done, a linux kernel load
is next (i.e. elfboot)
NOTE: 0x1000 needs to become a config variable, usable in CODE and
Makefiles.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@85 f3766cd6-281f-0410-b1cd-43a5c92072e9
include, we just put it here.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@84 f3766cd6-281f-0410-b1cd-43a5c92072e9
* seperate vsprintf to a seperate file as it was in v2.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@83 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@81 f3766cd6-281f-0410-b1cd-43a5c92072e9
This builds but dependencies need work; it takes a few
make -k
passes :-)
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@80 f3766cd6-281f-0410-b1cd-43a5c92072e9
It's slightly broken by the merge, but we want to get it in.
Will be fixed tomorrow.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@79 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@76 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@71 f3766cd6-281f-0410-b1cd-43a5c92072e9
file in LAR called raminit.
The intent is that stage0_i586.S would be common for just about all
stage0. It has no includes. We had to go with an ldscript.ld to deal
with the many bugs in binutils. Maybe someday this will change.
Tested by Ron and Uwe in bochs with debugging.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@68 f3766cd6-281f-0410-b1cd-43a5c92072e9
Use standard LinuxBIOS license header (trivial, no semantic changes).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@63 f3766cd6-281f-0410-b1cd-43a5c92072e9
accordance to the newboot document:
* reset vector (16 bytes)
* vpd (240bytes)
* boot block (8k - 256b)
* lar archive (256-8 k)
The boot block is kind of simple, still. It enables pmode, car, and
starts looking for an initram module in the lar archive.
Note: This doesnt do much at the moment,
as gas seems to produce buggy code in init.S.
Take this as a suggestion of how it might work and please provide
patches fixing it and bringing it into shape.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@62 f3766cd6-281f-0410-b1cd-43a5c92072e9
* add config.h so the Ron's latest changes build.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@60 f3766cd6-281f-0410-b1cd-43a5c92072e9
expect to hear about this change. Note that Stefan and I have discussed
this change and feel it is at least worth trying.
Also, please be aware that this change is backed by a
lot of experience with LinuxBIOS users and usage of the last 7 years.
First I detail changes, then I detail why.
Major changes for the new config system.
Selection of object files, and variable setting, is now controlled by
Kconfig.
There is only one dts now. It is in the mainboard file. It may later
move to the target file -- we will see.
The dts is in two parts, seperated by %%. The first part is a
fairly standard dts, and the dtc will automatically generate a device
tree from it. The device tree is composed of generic structures. These
structures are identical to those of the old V2 device tree. All the
hierarchy and parent/child/sibling relationships appear to be correctly
generated. This means that all the v2 code will work without change.
For each node in the tree, if the node has a property named 'config',
then the dtc will generate a reference to a structure and an include
directive for a path -- much as in the old Config tool.
Example: here is a fragment of a dts
==========
north {
config = "northbridge,intel,i440bx";
};
%%
struct northbridge_intel_i440bx_config north = {
.whatever = 1;
};
===========
The dtc will create:
#include <northbridge/intel/i440gx/config.h>
struct northbridge_intel_i440bx_config north = {
.whatever = 1;
};
struct device dev_north {
.chip_ops = &northbridge_intel_i440bx_ops;
.chip_info = &north;
.
.
.
};
So the programmer specifies the tree structure in dts form, indicates
which devices have a config entry, and sets up the C code for the
config. I have worked with this and am finding it very easy to use. I
think this is the way to go. Plus, we are getting rid of most of the
include hell of the old Config system.
Note that the config node is OPTTONAL! If you do not set it then no
structure usage/include will occur.
WHY?
Here is my setup for v3. I think this is good. I like it and am
finding it easy to work with.
Basically, the old config system combined makefile generation, tree
generation, and chip struct initialization in one file -- config.lb.
What we need are four things:
1. selection of .c files to build the bios with
2. the device tree -- this is built with generic structures defined in
include/device/device.h
3. The per-chip structures, usually defined in, e.g.,
northbridge/intel/i440bx/chip.h
4. setting of variables such as baud rate, etc.
Again, this was all done in Config.lb, spread all over the place, like this:
config chip.h
object superio.o
This was hard for people. So we moved the makefile stuff out into the
Kconfig system. This change eliminates (1) and (4) above.
OK, what's left? Well, with our plans from last October, we had device
object model tree stuff, AND still had chip struct initialization in
one file. (2) and (3) above. This is tough, because I was fighting the
mapping of DTS stuff to the C code. It was getting just as ugly as the
old Config.lb. I have been struggling with this for months and it just
wasn't going anywhere.
But it's way too hard to set up the device tree by hand -- I've tried
it. OTOH, it's really easy to set up the per-chip stuff by hand --
I've tried that too. I did a search via:
find ~/src/LinuxBIOSv2/src/ -name chip.h -print
and looked at them all. These files are really simple. There's no
reason to get too tricky, as there is nothing worth getting tricky
about. The problem is the device tree, not these simple chip info
structs.
So, here's the solution.
The ONLY dts is in the mainboard directory. There is no equivalent of
Config.lb in the south, north, cpu, all that stuff any more. The
Kconfig and Makefile in those directories replaced the build-related
functions of Config.lb.-- (1) and (4) above. The only thing left was
chip.h anyway (3) above.
But how can we express the settings in chip.h via the DTS? IT's been
very hard to get this going.
So, here is the trick. The dts in the mainboard directory divides into
two parts. The first part is the standard dts. The second part is the
C code. They are seperated, as in lex and yacc, with a %%.
Here is the dts for qemu (note that the cpus keyword is still not
right, and maybe this structure needs to change; i'm not that worried
about that too much, just the big picture I'm discussing here). Also,
note I'm working with some new properties, e.g. pcipath and pcidomain
-- if these properties exist ina node, then I create initialized
structure members for them. Also see enabled and on_mainboard --
properties, but I catch them and use them.
/{
cpus {
config="mainboard,emulation,qemu-i386";
emulation,qemu-i386@0{
enabled;
on_mainboard;
device_type = "cpu";
name = "emulation,qemu-i386";
pcidomain = "0";
/* the I/O stuff */
northbridge,intel,440bx{
pcipath = "0,0";
southbridge,intel,piix4{
};
};
};
};
};
%%
/* the user sets up these structs */
struct mainboard_emulation_qemu_i386_config cpus = {
.nothing = 1,
};
You can see the device tree stuff at top. If a given node has a
property named 'config', then that means what the old 'chip' thing
meant in Config.lb. The dtc will generate an #include to pull in a
file with the path name specified in the config property. The dtc will
not set up the per-chip struct, but it will set up a pointer to a
struct when it sets up the device tree. Note that at bottom, it's up
to you to set up the initialized struct. But this was always the easy
part anyway. Instead of wacky pseudo-C like we had in config.lb, we
just do real C. It's easy. Here is what the dtc generates.
#include <device/device.h>
#include <device/pci.h>
#include <mainboard/emulation/qemu-i386/config.h>
struct device dev_southbridge_intel_piix4;
struct device dev_northbridge_intel_440bx;
struct device dev_emulation_qemu_i386_0;
struct device dev_cpus;
struct device dev_root;
extern struct chip_operations mainboard_emulation_qemu_i386_ops;
struct mainboard_emulation_qemu_i386_config cpus = {
.nothing = 1,
};
struct device dev_root = {
.path = { .type = DEVICE_PATH_ROOT },
.links = 1,
.link = {
[0] = {
.dev = &dev_root,
.link = 0,
.children = &dev_cpus
},
},
.bus = &dev_root.link[0],
};
struct device dev_cpus = {
.chip_ops = &mainboard_emulation_qemu_i386_ops,
.chip_info = &cpus,
.links = 1,
.link = {
[0] = {
.dev = &dev_cpus,
.link = 0,
.children = &dev_emulation_qemu_i386_0
},
},
.bus = &dev_root.link[0],
.next = &dev_root,
};
struct device dev_emulation_qemu_i386_0 = {
.enabled = 1,
.on_mainboard = 1,
.path = {.type=DEVICE_PATH_PCI_DOMAIN,.u={.pci_domain={ .domain = 0 }}}
,
.links = 1,
.link = {
[0] = {
.dev = &dev_emulation_qemu_i386_0,
.link = 0,
.children = &dev_northbridge_intel_440bx
},
},
.bus = &dev_cpus.link[0],
.next = &dev_cpus,
};
struct device dev_northbridge_intel_440bx = {
.path = {.type=DEVICE_PATH_PCI,.u={.pci={ .devfn = PCI_DEVFN(0,0)}}},
.links = 1,
.link = {
[0] = {
.dev = &dev_northbridge_intel_440bx,
.link = 0,
.children = &dev_southbridge_intel_piix4
},
},
.bus = &dev_emulation_qemu_i386_0.link[0],
.next = &dev_emulation_qemu_i386_0,
};
struct device dev_southbridge_intel_piix4 = {
.bus = &dev_northbridge_intel_440bx.link[0],
.next = &dev_northbridge_intel_440bx,
};
This compiles just fine.
I think this is the right way to go, comments to me.
But, note, IT COMPILES. And it's simple. And, it will work with our
current device tree code!
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@59 f3766cd6-281f-0410-b1cd-43a5c92072e9
Trying to get dtc to compile correctly, getting errors from things I
don't understand.
So this happens:
[rminnich@q LinuxBIOSv3]$ make
CHK
/home/rminnich/src/bios/LinuxBIOSv3/include/linuxbios/version.h
building lzma
building initram
make: *** No rule to make target
`/home/rminnich/src/bios/LinuxBIOSv3/mainboard/"emulation/qemu-i386"/dts',
needed by `/home/rminnich/src/bios/LinuxBIOSv3/dtc.c'. Stop.
Until such time as others beside Stefan and I are committing, I am
auto-acking.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@56 f3766cd6-281f-0410-b1cd-43a5c92072e9
