Commit graph

18773 commits

Author SHA1 Message Date
Rizwan Qureshi
ae218ede69 UPSTREAM: driver/intel/fsp2_0: Make FSP-M binary XIP
If FSP_M_XIP is selected, then relocate FSP-M binary
while adding it in CBFS so that it can be executed in place.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16563
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I2579e8a9be06cfe8cc162337fb1064d15842229f
Reviewed-on: https://chromium-review.googlesource.com/385899
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15 13:41:21 -07:00
Martin Roth
60aa3f9eb0 UPSTREAM: cbmem: Exit with an errorlevel of 0 after printing help
cbmem --help should not return an error to the OS.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16574
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>

Change-Id: Id00091c679dbb109bc352cf8a81d67c2ae5666ec
Reviewed-on: https://chromium-review.googlesource.com/385898
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15 13:41:18 -07:00
Duncan Laurie
36c775ce26 UPSTREAM: drivers/i2c/tpm: Clean up handling of command ready
The TPM driver was largely ignoring the meaning of the command
ready bit in the status register, instead just arbitrarily
sending it at the end of every receive transaction.

Instead of doing this have the command ready bit be set at the
start of a transaction, and only clear it at the end of a
transaction if it is still set, in case of failure.

Also the cr50 function to wait for status and burst count was
not waiting the full 2s that the existing driver does so that
value is increased.  Also, during the probe routine a delay is
inserted after each status register read to ensure the TPM has
time to actually start up.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16591
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>

Change-Id: I1c66ea9849e6be537c7be06d57258f27c563c1c2
Reviewed-on: https://chromium-review.googlesource.com/385897
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15 13:41:16 -07:00
Duncan Laurie
862a23756a UPSTREAM: lpss_i2c: Add Kconfig option to enable debug
It is very useful to have the ability to see I2C transactions
performed by the host firmware.  This patch adds a simple
Kconfig option that will enable debug output.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16590
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I55f1ff273290e2f4fbfaea56091b2df3fc49fe61
Reviewed-on: https://chromium-review.googlesource.com/385896
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15 13:41:14 -07:00
Duncan Laurie
a3a42b67ef UPSTREAM: lpss_i2c: Change handling of controller enable/disable
This change modifies the lpss_i2c driver to behave more like
the Linux kernel driver.  In particular the controller is only
enabled when processing a transaction, and is disabled after.
This means that errors in one transaction will not affect later
transactions.

Also when disabling the controller the code is supposed to wait
on the enable bit in the "enable status" register and not in
the enable control register.  In order to get access to this
register the reg map was expanded to include all registers.

This was tested with the cr50 TPM driver to ensure that if a
transaction does fail that it can be successfully retried instead
of the bus being unusable.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16589
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I43a546d54996ba0f08550a801927b8f7a6690cda
Reviewed-on: https://chromium-review.googlesource.com/385095
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15 13:41:11 -07:00
Vaibhav Shankar
4f2a80a56c UPSTREAM: mainboard/intel/amenia: Configure PERST_0 pin
Configure PERST_0 and assign the pin in devicetree.

BUG=chrome-os-partner:55877
BRANCH=None

TEST=Suspend and resume using 'echo freeze > /sys/power/state'.
System should resume with PCIE and wifi functional.

Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/16350
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I39b4d8bba92f352ae121c7552f58480295b48aef
Reviewed-on: https://chromium-review.googlesource.com/385094
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15 13:41:09 -07:00
Sumeet Pawnikar
9fb32ce63f UPSTREAM: mainboards/apollolake: Set RAPL power limit PL1 value to 12W.
This patch sets tuned RAPL power limit PL1 value to
12W in acpi/dptf.asl for RAPL MSR register. With PL1
as 12W for WebGL and stream case, we measured SoC power
reaching upto 6W. Above 12W PL1 value, we observed that
Soc power going above 6W. With PL1 as 12W, system is
able to leverage full TDP capacity.

BUG=chrome-os-partner:56524
BRANCH=None

TEST=Built, booted on reef and verifed the package
power with heavy workload.

Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/16596
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I8185ce890f27e29bc138ea568af536bc274fe7b8
Reviewed-on: https://chromium-review.googlesource.com/385093
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15 13:41:07 -07:00
Sumeet Pawnikar
8cfc22f982 UPSTREAM: soc/intel/apollolake: Update PL1 value in RAPL MMIO register
Due to an incorrect value set for the power limit PL1, the
system is not able to leverage full TDP capacity. FSP code
sets the PL1 value as 6W in RAPL MMIO register based on
fused soc tdp value. This RAPL MMIO register is a physically
separate instance from RAPL MSR register. This patch sets
PL1 value to 15W in RAPL MMIO register.

BUG=chrome-os-partner:56524
BRANCH=None

TEST=Built, booted on reef and verifed the package power
with heavy workload.

Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/16595
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ib344247cd8d98ccce7c403e778cd87c13f168ce0
Reviewed-on: https://chromium-review.googlesource.com/383099
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15 13:41:05 -07:00
Vaibhav Shankar
3c17eef012 UPSTREAM: mainboard/google/reef: Configure PERST_0 pin
This configures PERST_0 in devicetree. For boards without
PERST_0, the pin should be disabled. For boards with PERST_0
the correct GPIO needs to be assigned.

BUG=chrome-os-partner:55877
BRANCH=None
TEST=None

Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/16603
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

Change-Id: I705009b480e02b4c9b2070bb4f82cb4d552e9a46
Reviewed-on: https://chromium-review.googlesource.com/385092
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15 13:41:02 -07:00
Vaibhav Shankar
f2e8ea4663 UPSTREAM: soc/intel/apollolake: Add PM methods to power gate PCIe
This implements GNVS variable to store the address of PERST_0,
_ON/_OFF methods to power gate PCIe during S0ix entry, and
PERST_0 assertion/de-assertion methods.

BUG=chrome-os-partner:55877
BRANCH=None

TEST=Suspend and resume using 'echo freeze > /sys/power/state'.
System should resume with PCIE and wifi functional.

Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/16351
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: I9f63ca0b8a6565b6d21deaa6d3dfa34678714c19
Reviewed-on: https://chromium-review.googlesource.com/385091
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15 13:41:00 -07:00
Aaron Durbin
5b8d0f68cd UPSTREAM: soc/intel/apollolake: initialize GNVS structure to 0
The code was not previously initializing the GNVS structure
to all 0's in the ACPI write tables path. Fix this and also
rearrange the ordering of updating the fields to only handle
the chip_info specific bits till last such that most of the
structure is filled in prior to bailing out in the case of a
bad devicetree.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16597
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: I7bdb305c6b87dac96af35b0c3b7524a17ce53962
Reviewed-on: https://chromium-review.googlesource.com/385090
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15 13:40:58 -07:00
Martin Roth
a65cabaaa7 UPSTREAM: SeaBIOS: Update stable version to 1.9.3
The SeaBIOS Stable version 1.9.3 was released back in July.  This has
just 4 fixes over 1.9.1:

fw/msr_feature_control: add support to set MSR_IA32_FEATURE_CONTROL
fw/pci: Add support for mapping Intel IGD via QEMU
fw/pci: add Q35 S3 support
build: fix .text section address alignment

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16254
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kevin O'Connor <kevin@koconnor.net>
Reviewed-by: Omar Pakker
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>

Change-Id: I527df85b5199942706d1188285c6678bf2f726a1
Reviewed-on: https://chromium-review.googlesource.com/385089
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15 13:40:55 -07:00
Gwendal Grignou
c9c2eabf09 UPSTREAM: mainboard/google/reef: add MKBP EC event as SCI event.
Add MKBP as a SCI event: the EC is then able to send events coming from
the sensors.

BUG=b:27849483
BRANCH=None

TEST=With EC configure to send MKBP events, check sensor information are
retrieved by the kernel.

Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://review.coreboot.org/16594
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ib06241bfcdc8567769baff4f3371cc0c6eab3944
Reviewed-on: https://chromium-review.googlesource.com/384341
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Gwendal Grignou <gwendal@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15 00:13:01 -07:00
Antonello Dettori
f6ab3922c7 UPSTREAM: i945.h: fix #include path
Fix the #include path.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16294
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: Ifefb2faef6e4fc87152acb21c37dd87e7c14645c
Reviewed-on: https://chromium-review.googlesource.com/385015
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15 00:12:59 -07:00
Antonello Dettori
120daa52d4 UPSTREAM: cpu/amd/family_10h-family_15h: transition away from device_t
Replace the use of the old device_t definition inside
cpu/amd/family_10h-family_15h.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16436
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: Ia1b155eeb7b67d94cf7aaa7789843a3e4ed3497a
Reviewed-on: https://chromium-review.googlesource.com/385014
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15 00:12:57 -07:00
Antonello Dettori
f1147d8d91 UPSTREAM: lenovo/t60: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/lenovo/t60.

The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16405
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I4d87498637d74f96ca5809b0e810755a58fc64ab
Reviewed-on: https://chromium-review.googlesource.com/385013
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15 00:12:54 -07:00
Antonello Dettori
ec3c4f92a1 UPSTREAM: southbridge/amd/agesa/hudson: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/amd/agesa/hudson.

The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16401
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I39cd2afe5e2b6ee3963fd3e949eab1db9e986d71
Reviewed-on: https://chromium-review.googlesource.com/385012
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15 00:12:52 -07:00
Antonello Dettori
5ef2f13870 UPSTREAM: northbridge/intel/nehalem: transition away from device_t
Replace the use of the old device_t definition inside
northbridge/intel/nehalem.

The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16406
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I6da4e0a9ef21b3285f4a369c8ddfbdb32a7a3801
Reviewed-on: https://chromium-review.googlesource.com/385011
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15 00:12:50 -07:00
Antonello Dettori
6decaef821 UPSTREAM: southbridge/intel/ibexpeak: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/intel/ibexpeak.

The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16408
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: Ic569aada9301b37e73196872584e191d553acd86
Reviewed-on: https://chromium-review.googlesource.com/385010
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15 00:12:47 -07:00
Antonello Dettori
96621527b0 UPSTREAM: southbridge/intel/i82801gx: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/intel/i82801gx.

The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16370
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: Ia257318a7068b54739f319bfbba35f2a07826940
Reviewed-on: https://chromium-review.googlesource.com/385009
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15 00:12:45 -07:00
Antonello Dettori
52bd94083a UPSTREAM: southbridge/intel/i82801ix: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/intel/i82801ix.

The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16403
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: Ibf20e6c08994b09d2a2e68a1a1d38a7a477493aa
Reviewed-on: https://chromium-review.googlesource.com/385008
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15 00:12:43 -07:00
Furquan Shaikh
90a2ccfb6b UPSTREAM: northbridge/intel/gm45: transation away from device_t
Replace the use of the old device_t definition inside
northbridge/intel/gm45.

The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16402
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I87754799f922cf241fb456071bac04e6fe1eab34
Reviewed-on: https://chromium-review.googlesource.com/385007
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15 00:12:40 -07:00
Antonello Dettori
7034031215 UPSTREAM: southbridge/via/vt8237r: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/via/vt8237r.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16489
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I9c1211e698ef35f56dd71c2c021dea680091c1ee
Reviewed-on: https://chromium-review.googlesource.com/385006
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15 00:12:38 -07:00
Antonello Dettori
d38defa96c UPSTREAM: southbridge/sis/sis966: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/sis/sis966.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16488
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I9e731fedc6f21eaa2685f794ea2172eb4800628b
Reviewed-on: https://chromium-review.googlesource.com/385005
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-14 13:04:43 -07:00
Antonello Dettori
2ccf4d85d5 UPSTREAM: southbridge/nvidia/mcp55: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/nvidia/mcp55.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16487
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I98ac468940eaf6c456fa95540ec3e718edfe26a7
Reviewed-on: https://chromium-review.googlesource.com/385004
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-14 13:04:41 -07:00
Antonello Dettori
3425de7de4 UPSTREAM: southbridge/nvidia/ck804: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/nvidia/ck801.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16486
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I43d4d2175f0b6b9e7e2e6fe665ba3d99d792427c
Reviewed-on: https://chromium-review.googlesource.com/385003
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-14 13:04:38 -07:00
Antonello Dettori
1768aec112 UPSTREAM: southbridge/amd/sb800: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/amd/sb800.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16480
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I488cde4504128331106f50b34869905e30f5ab83
Reviewed-on: https://chromium-review.googlesource.com/385002
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-14 13:04:36 -07:00
Antonello Dettori
e3a15916e6 UPSTREAM: southbridge/amd/sb700: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/amd/sb700.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16479
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I44b0be2070719066dd18bbf2882c417caef5d8b2
Reviewed-on: https://chromium-review.googlesource.com/385001
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-14 13:04:34 -07:00
Antonello Dettori
5698604391 UPSTREAM: southbridge/amd/sb600: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/amd/sb600.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16478
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I0227cc0c611324f513f8170c9d8819a88af39b39
Reviewed-on: https://chromium-review.googlesource.com/385000
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-14 13:04:32 -07:00
Antonello Dettori
e458b2ccab UPSTREAM: southbridge/amd/rs780: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/amd/rs780.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16477
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: Ia9929baeec7423e9e2f06324038ddfbec006beb7
Reviewed-on: https://chromium-review.googlesource.com/384999
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-14 13:04:29 -07:00
Antonello Dettori
a9ab52c937 UPSTREAM: southbridge/amd/rs690: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/amd/rs690.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16476
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: Ief43393f62312bfe82e960faf56b1e2ec048f4ff
Reviewed-on: https://chromium-review.googlesource.com/384998
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-14 13:04:27 -07:00
Antonello Dettori
6a340ad47f UPSTREAM: southbridge/amd/pi/hudson: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/amd/pi/hudson.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16475
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I8b22a8d9f0e90afaf0f218c5c0924a78883b7498
Reviewed-on: https://chromium-review.googlesource.com/384997
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-14 13:04:25 -07:00
Antonello Dettori
e80b700f36 UPSTREAM: southbridge/amd/cimx: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/amd/cimx.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16474
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: Ibe2766b956b0ca02be63621aee9a230b16d9923b
Reviewed-on: https://chromium-review.googlesource.com/384996
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-14 13:04:22 -07:00
Jianqun Xu
d84bf25b3e rockchip: rk3399: improve write leveling flow
To improve sdram 800MHz and 933MHz stability, we
need to modify write leveling flow, to get the
more proper write leveling value.

BUG=chrome-os-partner:56940
BRANCH=none
TEST=Boot from kevin on 933MHz, and do stressapptest

Change-Id: I87efddf628c3683fcb85d6875e029cf3cbc482be
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/384292
Commit-Ready: Julius Werner <jwerner@chromium.org>
Tested-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-09-13 22:22:02 -07:00
Julius Werner
05efb82ca0 google/gru: Shrink RW_ELOG region to 4KB
Since there's currently a limitation in coreboot's code that prevents
more than 4KB to be used by the eventlog anyway, this patch shrinks the
available RW_ELOG area in the FMAP for Gru down to 4KB. This may prove
prudent later if we ever resolve that limitation, so that tools can rely
on the area in the FMAP being the same as the area actually used by the
read-only firmware code on these boards.

BRANCH=gru
BUG=chrome-os-partner:55593
TEST=Booted Kevin, confirmed that eventlog got written normally. Ran a
reboot loop to exhaust eventlog space, confirmed that the shrink code
kicks in as expected before reaching 4KB.

Change-Id: Ia2617681f9394e953f5beb4abf419fe8d97e6d3e
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/384585
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Simon Glass <sjg@google.com>
2016-09-13 22:21:29 -07:00
Julius Werner
1d4c6c6f6c rockchip/rk3399: Move TTB to the end of SRAM
We found that we may want to load some components of BL31 on the RK3399
into SRAM. As usual, these components may not overlap any coreboot
regions still in use at that time, as is already statically checked by
the check-ramstage-overlaps rule in Makefile.inc.

On RK3399, the only such regions are TTB and STACK. This patch moves the
TTB region back to the end of SRAM (right before STACK), so that a large
contiguous region of SRAM before that remains usable for BL31.

BRANCH=gru
BUG=None
TEST=Booted Kevin.

Change-Id: I37c94f2460ef63aec4526caabe58f35ae851bab0
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/384635
Reviewed-by: Simon Glass <sjg@google.com>
2016-09-13 22:21:27 -07:00
Antonello Dettori
e4e73bf256 UPSTREAM: southbridge/amd/amd8111: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/amd/amd8111.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16473
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I76cdc32171b7ce819b53c534b3a5e57e9dd5f3dd
Reviewed-on: https://chromium-review.googlesource.com/384995
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-13 22:21:15 -07:00
Antonello Dettori
aba8f678d2 UPSTREAM: northbridge/amd/amdht: transition away from device_t
Replace the use of the old device_t definition inside
northbridge/amd/amdht.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16468
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I7dfb8f001504c691aeddf1bfbc3be05cc7d31ce4
Reviewed-on: https://chromium-review.googlesource.com/384994
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-13 22:21:13 -07:00
Antonello Dettori
0a1383c351 UPSTREAM: northbridge/amd/amdk8: transition away from device_t
Replace the use of the old device_t definition inside
northbridge/amd/amdk8.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16467
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I5209dd309f0685f83d8a468c50309d5fda77973a
Reviewed-on: https://chromium-review.googlesource.com/384993
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-13 22:21:10 -07:00
Antonello Dettori
acf1bcd3aa UPSTREAM: northbridge/amd/amdfam10: transition away from device_t
Replace the use of the old device_t definition inside
northbridge/amd/amdfam10.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16466
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I5037feb31c51d06ccc672b0771d5d6e8c0dac949
Reviewed-on: https://chromium-review.googlesource.com/384992
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-13 22:21:08 -07:00
Antonello Dettori
e78858a6c8 UPSTREAM: mainboard/bcom/winnetp680: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/bcom/winnetp680.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16465
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I6f57a669f83bed190e90e1b7be01f8c886546e2e
Reviewed-on: https://chromium-review.googlesource.com/384991
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-13 22:21:05 -07:00
Antonello Dettori
b30abc87b1 UPSTREAM: mainboard/gigabyte/*: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/gigabyte/*.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16439
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: Ied62d6234a4f6ea5f851e98a098b2c8f4e3db144
Reviewed-on: https://chromium-review.googlesource.com/384990
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-13 22:21:03 -07:00
Antonello Dettori
28e64ef4ff UPSTREAM: mainboard/asus/*: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/asus/*.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16438
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I5ddfba2102854adcc9bbfd75f7acbe76f0152b72
Reviewed-on: https://chromium-review.googlesource.com/384989
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-13 22:21:01 -07:00
Hakim Giydan
275efb9ae6 UPSTREAM: soc/marvell/mvmap2315: Add DDR driver
This driver is only a prototype driver, real driver
will be integrated at a later time.

Testing: booted successfully.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/16554
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I372764962e96e5c9c827d524bc369978c5c1fda8
Reviewed-on: https://chromium-review.googlesource.com/384988
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-13 22:20:58 -07:00
Hakim Giydan
5e3c372975 UPSTREAM: soc/marvell/mvmap2315: Add MCU driver
Testing: booted successfully.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/15529
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I003f6929b00476d46be931773cd35418fe6622a6
Reviewed-on: https://chromium-review.googlesource.com/384987
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-13 22:20:56 -07:00
Hakim Giydan
f4e37e826f UPSTREAM: soc/marvell/mvmap2315: Add WDT driver
Testing: booted successfully.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/15519
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: Ie9c9297f321c838f86e5536aab29f67a0eeb053d
Reviewed-on: https://chromium-review.googlesource.com/384986
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-13 22:20:54 -07:00
Hakim Giydan
644129a148 UPSTREAM: soc/marvell/mvmap2315: Add NVM driver
This driver uses BootROM callback to read and write
to the nvm using I2C.

Testing: booted successfully.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/16161
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I8639af3e004f6631d7e596507c106159835f979f
Reviewed-on: https://chromium-review.googlesource.com/384985
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-13 22:20:52 -07:00
Hakim Giydan
42af98cab9 UPSTREAM: soc/marvell/mvmap2315: Add A2BUS driver
A2BUS is a custom fabric.

Testing: booted successfully.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/15523
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: If6e61f5aa30217eb601ac460d9306166b8433569
Reviewed-on: https://chromium-review.googlesource.com/384984
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-13 22:20:49 -07:00
Hakim Giydan
964f6395d0 UPSTREAM: soc/marvell/mvmap2315: Add PMIC driver
Testing: booted successfully.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/16149
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I168206585f403d2259efe424e563982be661df0b
Reviewed-on: https://chromium-review.googlesource.com/384983
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-13 22:20:47 -07:00
Hakim Giydan
068c970274 UPSTREAM: soc/marvell/mvmap2315: Add APMU driver
APMU is the AP power management unit.
It is a separate processor that handles enabling
individual power rails.

This driver handles sending and receiving commands
from/to APMU.

Testing: booted successfully.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/15518
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I5ae07849f8432bece8a0ae9066a3f786e6e8d2fe
Reviewed-on: https://chromium-review.googlesource.com/384982
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-13 22:20:45 -07:00