Add "(LB) " to all log messages to differentiate them visually
from the rest of the boot messages. This is similar to what
Xen does when booting (it prefixes all log messages with "(XEN) ").
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@209 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@205 f3766cd6-281f-0410-b1cd-43a5c92072e9
it via Kconfig (select box with some common values).
The default is 256 KB.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@196 f3766cd6-281f-0410-b1cd-43a5c92072e9
Comitting IP checksum code, and its usage in linuxbios table creation.
Mods to the dts, so that the device ops for the domain are set to the
proper structure. This change is important. It gets rid of the obscure,
confusing use of the enable_dev function to pick the right ops for a
device. It makes the ops initilization very clear at the top level, in
the dts. This has been tested and works, linux boots on Bochs under
this version.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@191 f3766cd6-281f-0410-b1cd-43a5c92072e9
code (This goes hand in hand, as some parts of serial were hardcoded
to one architecture until now)
* include/uart8250.h: add TTYSx defines that are used in
multiple places. formerly part of arch/x86/serial.c.
Drop init_uart8250 (unused)
* lib/uart8250.c: drop arch/x86/config.h usage
Drop init_uart8250 (unused)
* arch/powerpc/Kconfig, arch/x86/Kconfig: add CONFIG_ARCH to
contain the directory name under LinuxBIOSv3/arch/
* arch/x86/console.c: drop some dead code. Drop hardcoded config.h values.
use generic uart8250.h header
* arch/x86/cachemain.c: Drop hardcoded config.h values. Still use hardcoded
ROM size for now. (To be changed later)
* arch/x86/config.h: dropped, no longer needed
* arch/x86/serial.c: factor out generically used defines to uart8250.h
* Makefile: use mainboard architecture instead of target architecture to choose
include path.
Read .xcompile if available (configure replacement).
Create build.h with compile time and version.
* util/xcompile/xcompile: new file. Search for supported cross compilers
linkers, assemblers (and potentially supported compiler flags etc)
This is a very slick configure replacement.
* util/dtc/Makefile: fix Makefile for cross compilation
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@190 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@186 f3766cd6-281f-0410-b1cd-43a5c92072e9
memory. qemu does not, which is odd.
in bochs, we get this.
find_lb_table: header test: L I I O
find_lb_table: Found candidate at: 00000500
find_lb_table: header checksum o.k.
find_lb_table: table checksum o.k.
find_lb_table: record count o.k.
collect_linuxbios_info: collect_linuxbios_info: yes
collect_linuxbios_info: Found LinuxBIOS table at: 00000500
malloc_diag: alloc: 0 bytes (0 blocks), free: 16376 bytes (1 blocks)
malloc_diag: alloc: 72 bytes (1 blocks), free: 16304 bytes (1 blocks)
convert_memmap: 0x00000000000000 0x000000000005a4 16
convert_memmap: 0x000000000005a4 0x000000000efa5c 1
convert_memmap: 0x000000000f0000 0x00000001f10000 1
convert_memmap: 0x000000000f0000 0x00000000000000 16
collect_sys_info: after collect info->memrange 00119418
collect_sys_info: 00000000000005a4-00000000000f0000
collect_sys_info: 00000000000f0000-0000000002000000
collect_sys_info: RAM 32 MB
Some further changes are coming, aimed at making it easier for people to
understand how things fit together.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@185 f3766cd6-281f-0410-b1cd-43a5c92072e9
add debug printks.
make dtc put 'root' as the first_node, instead of making the last node
be the first node .... much happier in linuxbios.
sprintf is broken ... dammit. I hope someone will fix it. I've got about
another week of full-time I can spend on this and then I go back to part
time. So I'm going to need some help soon.
other fixups, and also, make the dts conform to the needs of the device
tree. So we have a domain0 and a device (0,0) that is the north.
Mostly things are working, but we're STILL not getting any memory in the
LB tables from the north. The device tree is a bitch.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@175 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@172 f3766cd6-281f-0410-b1cd-43a5c92072e9
DEFAULT_CONSOLE_LOGLEVEL is now set via xconfig.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@167 f3766cd6-281f-0410-b1cd-43a5c92072e9
Some minor cosmetic fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@155 f3766cd6-281f-0410-b1cd-43a5c92072e9
are undefined (trivial).
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@151 f3766cd6-281f-0410-b1cd-43a5c92072e9
Plus some small trivial reformatting of comments in stage0_i586.S
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@146 f3766cd6-281f-0410-b1cd-43a5c92072e9
discussion. There was obviously an earlier version by Eric which I have
not looked at before writing thios one. See rev 2131 in v2.
Trivial, thus self-acked.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@140 f3766cd6-281f-0410-b1cd-43a5c92072e9
renamed the phase3 etc. to stuff like phase3_scan, so you can get a
rought idea what it is. The names mean more.
adding pci_device and, at the same time, showing how we can get rid of
the really ugly stuff that crept in. note you can specify ops in the
dts, which avoids the need for hideous stuff like this:
static void enable_dev(struct device *dev)
{
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
dev->ops = &pci_domain_ops;
pci_set_method(dev);
}
else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
dev->ops = &cpu_bus_ops;
}
}
So that foolishness is gone.
added delay functions.
Note that we have include/lib.h, and define all the functions in there,
instead of in lots of fiddly includes.
Brought back the enable op, once I understood it; renamed it to
something that makes sense.
I'll be on a plane soon, will continue to work, but at least you can see
what's going on here.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@139 f3766cd6-281f-0410-b1cd-43a5c92072e9
because not all emulators get the ram size registers right, or so we
hear.
This northbridge is still incomplete. We are not just copying the v2
one, as we are trying to undo the various hacks that crept in over the
years, due to limitations in the v2 device model. Just look at the
i440bx in v2 and you can see what I mean. We are working to find a
better way to get the job done than those hacks. They are just too
confusing for people to follow.
add an include for the northbridge makefile into the qemu Makefile.
Re-order the includes in arch/x86/Makefile so we can pick up .o files
from other places. Add a STAGE2_CHIPSET_OBJ for objects defined in those
makefiles included in mainboard.
Current issues: the enable_dev function for the i440bx is not getting
called. Enable_dev should be renamed to phase3_setup or something that
actually means something. The name as it is is totally useless.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@138 f3766cd6-281f-0410-b1cd-43a5c92072e9
start documenting the device model -- since it is clear to me from
reading v2 that not even the v2 guys totally got it
call write_tables in stage2
fix the makefile to put stage2.o first to make sure it gets
called.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@135 f3766cd6-281f-0410-b1cd-43a5c92072e9
I was meaning to check in more, but I lost 4h of work due to some ext3
problem. Bummer I believed those saying its more stable than reiserfs.
Signed-off-by: Stefan Reinauer <stepan@openbios.org>
Acked-by: Stefan Reinauer <stepan@openbios.org>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@134 f3766cd6-281f-0410-b1cd-43a5c92072e9
Remaining to be done:
PIRQ table
MP table
ACPI table
relocate the GDT reload to a sensible place -- or figure out if we even
need to bother; we're back to execute in place and the GDT is in flash
rom ==> we can leave it until we boot the payload I think.
At this point, however, we've got the basic bits to sensibly create
tables.
This has been tested and works on bochs.
It is working to a point, but still failing on qemu for reasons we don't
quite understand.
Elfboot
Found ELF candidate at offset 0
New segment addr 0x100000 size 0x21310 offset 0xc0 filesize 0x7348
(cleaned up) New segment addr 0x100000 size 0x7348 offset 0xc0
set 00100000 to 0 for 0 bytes
Copy to 00100000 from fffc3f24 for 29512 bytes
New segment addr 0x121320 size 0x48 offset 0x7420 filesize 0x48
(cleaned up) New segment addr 0x121320 size 0x48 offset 0x7420
set 00121320 to 0 for 0 bytes
Copy to 00121320 from fffcb284 for 72 bytes
Dropping non PT_LOAD segment
Dropping non PT_LOAD segment
Jumping to boot code at 0x1047c0
FILO version 0.5 (rminnich@q.ccstar.lanl.gov) Sun Feb 25 10:19:16 MST
2007
collect_sys_info: boot eax = 0xfe
collect_sys_info: boot ebx = 0xffffd4ca
collect_sys_info: boot arg = 0x1047c0
collect_linuxbios_info: NOT Searching for LinuxBIOS tables...
Can't get memory map from firmware. Using hardcoded default.
collect_sys_info: 0000000000000000-00000000000a0000
collect_sys_info: 0000000000100000-0000000002000000
collect_sys_info: RAM 32 MB
relocate: Current location: 0x1000c7-0x12142e
relocate: Relocating to 0x1fdec90-0x1fffff7... ok
Press <Enter> for default boot, or <Esc> for boot prompt...
boot: hdc1:/phase1 root=/dev/hdc1 console=ttyS0,115200
malloc_check: invalid head->prev_size: 0x0
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@133 f3766cd6-281f-0410-b1cd-43a5c92072e9
resource .c functions -- sigh -- this will be next.
fix types, fix some usage, but we do not yet generate pirqi, mptables,
or acpi. This will be next.
This code will be called from phase6 in stage 2, and probably
attached to a cpu. Or, it will be inline in the stage2.c code, since
the need for tables is generic.
I'm also going to move the cryptic usage of lgdt from here to stage 2,
phase 2, of the cpu code. The device model improvements are making it
easier to think about when things happen, we are finding.
I'm going to get lunch and go see some of brussels. It's a miserable day
but ...
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@130 f3766cd6-281f-0410-b1cd-43a5c92072e9
commit. adding support for tables.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@129 f3766cd6-281f-0410-b1cd-43a5c92072e9
We have merged the plethora of include files into one. A given linuxbios
target architecture must support all the functions described therein.
All the structs etc. in include/tables.h are known to be
architecture-independent.
We hope this new layout is easier to folow than the old one.
Todo: Remove the LGDT code from tables writing (how did THAT get in
there ;-) and put it somewhere sane; add OFW table support. We are going
to need some nice OFW table code.
Also, the license headers should be correct in this commit.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@128 f3766cd6-281f-0410-b1cd-43a5c92072e9
warnings for developing/debugging, but not for the default LinuxBIOS build.
These are purely cosmetic changes, no build process changes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@126 f3766cd6-281f-0410-b1cd-43a5c92072e9
minute.
This code has been tested; we are booting filo from flash in qemu at
this point.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@114 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@111 f3766cd6-281f-0410-b1cd-43a5c92072e9
Press <Enter> for default boot, or <Esc> for boot prompt... timed out
boot: hdc1:/phase1 root=/dev/hdc1 console=ttyS0,115200
malloc_diag: alloc: 112 bytes (3 blocks), free: 16264 bytes (1 blocks)
malloc_diag: alloc: 128 bytes (4 blocks), free: 16248 bytes (1 blocks)
file_open: dev=hdc1, path=/phase1
find_ide_controller: PCI IDE #0 not found
IDE channel 1 not found
devopen: failed to open ide
malloc_diag: alloc: 112 bytes (3 blocks), free: 16264 bytes (1 blocks)
malloc_diag: alloc: 48 bytes (2 blocks), free: 16328 bytes (1 blocks)
boot: hdc1:/phase1 root=/dev/hdc1 console=ttyS0,115200
So we've just booted our first payload in V3!
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@110 f3766cd6-281f-0410-b1cd-43a5c92072e9
FLASH. It is far simpler than before.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@109 f3766cd6-281f-0410-b1cd-43a5c92072e9
of FLASH. Since it runs out of FLASH, we have removed the need for
bounce buffer support. that in turn rips out all kinds of stuff, so it
is now simpler. We're ripping out all the checksum stuff -- lar does
that.
lar.c has some debug prints removed.
elfboot.c has some mods, but elfboot.c is going away.
cachemain.c has a few mods for using newelfboot.
Makefile reflects these changes.
Not tested, I'm going to bed though, so here you are.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@108 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@107 f3766cd6-281f-0410-b1cd-43a5c92072e9
other stages, give it 16k instead of 8
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@106 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@105 f3766cd6-281f-0410-b1cd-43a5c92072e9
* add license header to console/vtxprintf.c and arch/x86/serial.c
* clean out dead code from console/vtxprintf.c
* adapt arch/x86/serial.c to CONFIG_ stuff
* actually include config.h in CFLAGS
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@104 f3766cd6-281f-0410-b1cd-43a5c92072e9
Oddly, this error just appeared, due to clashing commits.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@103 f3766cd6-281f-0410-b1cd-43a5c92072e9
We're trying to avoid the bounce buffer mess, which is really complex,
by running elfboot out of the boot block. This code includes a really
dumb allocator in elfboot which may or may not work. It basically
allocates off the elfboot() stack.
This builds, but elfboot is not tested. That's next.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@102 f3766cd6-281f-0410-b1cd-43a5c92072e9
call it something more useful than boot.c
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@100 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@99 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@97 f3766cd6-281f-0410-b1cd-43a5c92072e9
Some updates to the docs, but these will change more.
add memcmp. Crude implementation, but it really does not matter.
add compute_ip_checksum.c
mods to elfboot. Thanks to our new design, BOUNCE BUFFERS ARE DEAD. Yee
ha!
updates to makefile
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@96 f3766cd6-281f-0410-b1cd-43a5c92072e9
* remove some warnings
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@95 f3766cd6-281f-0410-b1cd-43a5c92072e9
