- Remove the "MISSING_SPACE" check which checks for breaks at a space in
a string concatenation. Most of the time this makes sense, but we
occasionally need to break where there isn't a space, so having a hard
rule doesn't always work.
- Don't check the vendorcode directory for compliance to coreboot's
code format rules.
BUG=none
BRANCH=none
TEST=none
Change-Id: If6648109dac8e91066f03e8d3c733db2f239b978
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2e17eaed1b
Original-Change-Id: Ic07677b19520b5d22363834c77f5dee7bba9e429
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18569
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/452365
checkpatch: add option for excluding directories
when importing code from external sources
Using --exclude <dir> we should be able to exclude a list of well
defined locations in the tree that carry sources from other projects
with other styles.
This comes from the 01org/zephyr project in github:
Original-Change-Id: I7d321e85eed6bc37d5c6879ae88e21d20028a433
Original-Signed-off-by: Anas Nashif <anas.nashif@intel.com>
BUG=none
BRANCH=none
TEST=none
Change-Id: Ifdd76bc8f440e6cbb478fabd3b1a7bce55d1009f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a3cac87ea8
Original-Change-Id: Icc9e841e7d84026d6ab857ff90b0f093515ccaad
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18568
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/452364
Fix the following errors detected by checkpatch.pl:
ERROR: space prohibited after that open parenthesis '('
ERROR: space prohibited before that close parenthesis ')'
TEST=Build and run on Galileo Gen2
Change-Id: I06aa831a79cb531d5b7042b72950c7a79fe445c4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d638ef4ec4
Original-Change-Id: I586c5731c080282080fe5ddf3ac82252cb35bdd4
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18636
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/452363
The event log entry indicating developer mode is useful for the
boot path, but is not really useful on the resume path and removing
it makes the event log easier to read when developer mode is enabled.
To make this work I have to use #ifdef around the ACPI code since
this is shared with ARM which does not have acpi.h.
BUG=b:36042662
BRANCH=none
TEST=perform suspend/resume on Eve and check that the event log
does not have an entry for Chrome OS Developer Mode.
Change-Id: Ief6dead73856689f0fb0bce6266d66c7196340ee
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f8401cddb8
Original-Change-Id: I1a9d775d18e794b41c3d701e5211c238a888501a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18665
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452361
If Deep Sx is enabled the event log will get entries added on every
power sequence transition indicating that the suspend well has failed.
When a board is using Deep Sx by design this is intended behavior and
just fills the logs with extraneous events.
To make this work the device init state has to be executed first so it
actually enables the Deep Sx policies in the SOC since this code does
not have any hooks back into the devicetree to read the intended setting
from there.
BUG=b:36042662
BRANCH=none
TEST=Perform suspend/resume on Eve device with Deep S3 enabled, and
then check the event log to be sure that it does not contain the
"SUS Power Fail" event.
Change-Id: I8455c68e305a3c098d6a823c1586a8db77c88666
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ac2cbd0ffb
Original-Change-Id: I3c8242baa63685232025e1dfef5595ec0ec6d14a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18664
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/452360
Add a function to read the current state of Deep S5 configuration
and indicate if it is enabled (for AC and/or DC) or disabled.
This is similar to the existing function that checks Deep S3
enable state.
BUG=b:36042662
BRANCH=none
TEST=tested with subsequent commits to check Deep S5 state at boot
and filter event log messages if it is enabled.
Change-Id: I5aaa847908d0ab3468310e69414a08875777a78f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cb76d50f0d
Original-Change-Id: I4b60fb99a99952cb3ca6be29f257bb5894ff5a52
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18663
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/452359
Add options to the skylake chip config that will allow tuning the
various settings that can affect acoustics with the CPU and its VRs.
These settings are applied inside FSP, and they can adjust the slew
slew rate when changing voltages or disable fast C-state ramping on
the various CPU VR rails.
BUG=b:35581264
BRANCH=none
TEST=these are currently unused, but I verified that enabling the
options can affect the acoustics of a system at runtime.
Change-Id: I9445eb29c9f3089f68f1445fce8fb50464bf10cf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b2aac85030
Original-Change-Id: I6a8ec0b8d3bd38b330cb4836bfa5bbbfc87dc3fb
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18662
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452358
A new board revision is making use of two previously unused GPIOs
to drive BOOT/RESET pins to an on-board MCU.
The reset pin is open drain so it is set as input by default, and
the boot pin is driven low by default.
Since these are UART0 pins they also need to be set up again after
executing FSP-S as it will change them back to native mode pins.
BUG=b:36025702
BRANCH=none
TEST=manual testing on reworked board, toggling GPIOs to put
the MCU into programming mode.
Change-Id: I3f6facc48a380e3e72e6832f9a5a9a1730d2f935
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 03df460af5
Original-Change-Id: Id6f0ef2f863bc1e873b58e344446038786b59d25
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18661
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452357
Allows to use SSE and floating point in payloads without digging to
much into x86 assembly code.
Tested on Lenovo T500 (Intel Core2Duo).
Both floating point operation and SSE is properly working.
BUG=none
BRANCH=none
TEST=none
Change-Id: I5869905873f0bacfeb38d7e81d25d956a676ffb5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b854ae2649
Original-Change-Id: I4a5fc633f158de421b70435a8bfdc0dcaa504c72
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/18345
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/451619
Fine tune USB2, need to override the following registers.
port#1:
PERPORTPETXISET=7
PERPORTTXISET=0
BUG=b:35858164
BRANCH=reef
TEST=built, measured eye diagram on snappy, and reviewed by intel
Change-Id: Ic4964e78338cb6d00d8d2dd61d627870ad656882
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e4c85c128a
Original-Change-Id: I461cf8f032b4e70abc9707e6cd3603a62cee448f
Original-Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Original-Reviewed-on: https://review.coreboot.org/18590
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/451617
This adds support for the Wildcat Point LP for intelmetool.
When the tool detected a Wildcat Point LP,
then the ME will be reported as difficult-to-remove.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib1fda21126fa807d0b8e1a9e5a90120424bcc9bc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8c247a2a79
Original-Change-Id: I35423db11cdc1e21e7f02ce90dace7fb4d236c45
Original-Signed-off-by: Huan Truong <htruong@tnhh.net>
Original-Reviewed-on: https://review.coreboot.org/18575
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/451436
The intel ME checker tool would segfault if it reaches the end of
the loop without having the dev pointer set. This happens when
it gets to the end of the previous loop without knowing what to do
with any of the devices it sees.
This patch makes sure the pointer is not NULL before accessing it.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibaef27c8be18b6704d60250098a6f676fe197965
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2a1ae05316
Original-Change-Id: Ia13191799d7e00185947f9df5188cb2666c43e2a
Original-Signed-off-by: Huan Truong <htruong@tnhh.net>
Original-Reviewed-on: https://review.coreboot.org/18573
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/451435
- Fix whitespace: Change some spaces to tabs
- Add myself as an abuild maintainer
- Add util/xcompile and util/genbuild_h to the BUILD SYSTEM section
- Add new sections for utilities: docker, toolchain, and git
- Remove GENERIC DRAM section
- Remove the mailing list. We don't want it to be added as a reviewer.
BUG=none
BRANCH=none
TEST=none
Change-Id: I2dfae1e05e38a8d5bdba90cc5460f3ada6727ce1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 954338d21b
Original-Change-Id: I78692fcac174d7b7c4d65911c85e4e2dacefcfc0
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18578
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/451434
No board with binaryPI currently supports HAVE_ACPI_RESUME. For
platforms with PSP the approach is also very different from what
we previously had here.
Furthermore, s3_resume.[ch] files under cpu/amd/pi do not
distinguish between NonVolatile and Volatile buffers of S3 storage.
This means the Volatile buffer that is maintained and available in
CBMEM is unnecessarily copied to SPI flash. This has been fixed on
open-source AGESA directory, so development of S3 suspend support
with binaryPI is better continued with that.
Unfortunately there are further complications and indications that
open-source AGESA may have always had a low-memory corruption
issue. This has to be investigated separately before restoring
or claiming S3 is supported on binaryPI.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iaa3b5135ab114cd1e0dcd540ed8df3adee235dcf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 97a4b3edf0
Original-Change-Id: I81585fff7aae7bcdd55e5e95bc373e0adef43ef0
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18501
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-on: https://chromium-review.googlesource.com/451433
None of the boards currently have HAVE_ACPI_RESUME and
and ACPI S3 support calls should not appear under board
directories anyways.
BUG=none
BRANCH=none
TEST=none
Change-Id: I9b9d34bc46a403431f24abe42d1180a6cca6841c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1b183aa6ce
Original-Change-Id: I1abd40ddba64be25b823abf801988863950c1eb5
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18500
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-on: https://chromium-review.googlesource.com/451432
The file is used for fam15.
BUG=none
BRANCH=none
TEST=none
Change-Id: I52a113c24020e70ae237a97661ced1310c6f6185
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3444a9d716
Original-Change-Id: I7cdf238a8f7be4bf79546bcfc3c9d05bd8986e3e
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18635
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-on: https://chromium-review.googlesource.com/451431
Definitions are not part of ACPI S3 feature, nor do
they require any AGESA headers so move them to a
better location.
BUG=none
BRANCH=none
TEST=none
Change-Id: Icb4e2a24f724cf12b9891e9a73a5683972155994
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: da74041b2b
Original-Change-Id: I9269e9d65463463d9b8280936cf90ef76711ed4f
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18616
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-on: https://chromium-review.googlesource.com/451430
Declaration of main in cpu/amd/car.h conflicts with the
definition of main required for x86/postcar.c in main_decl.h.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iedbb3818068b7a24d35057537eccd385da58383b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8e1f908ce0
Original-Change-Id: I19507b89a1e2ecf88ca574c560d4a9e9a3756f37
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18615
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/451429
Note that M and M_PRO had same DefaultPlatformMemoryConfiguration
defined, use one for both.
BUG=none
BRANCH=none
TEST=none
Change-Id: I48094b6411cfb50ecf026bc5ba02c89b308d994f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 07bc9f76bc
Original-Change-Id: Ia1925957800a7fe6ef511b2d041f7a863c8fc931
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18606
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/451428
Relocate the enabling of the LAPIC out of the southbridge source and
surround it with a check for CONFIG_UDELAY_LAPIC (typical for AMD
systems). The LAPIC is now enabled for all cores; not only the BSP,
and not only when the UART is used.
This solves the problem of APs not having their APICs enabled when
the timer is expected to be functional, e.g. verstage often uses
do_printk_va_list() instead of do_printk() which exits early for
APs when CONFIG_SQUELCH_EARLY_SMP=y.
The changes were tested with two Gardenia builds, one using verstage
and another with CONFIG_SQUELCH_EARLY_SMP=n.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 93ffc311165f19d4192a5489051fa4264cd8e0ad)
BUG=none
BRANCH=none
TEST=none
Change-Id: I3b2cf63f46cb63e46ddc916f399de7f9e76759e1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 03e6a455a3
Original-Change-Id: Ieaecc0bf921ee0d2691a8082f2431ea4d0c33749
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18436
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/451427
Only declare S3 support in ACPI if CONFIG_HAVE_ACPI_RESUME
is set.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7c1ebe9516b26c9f4a9d78ee224c2057238c66a6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a0891ee367
Original-Change-Id: I6f8f62a92478f3db5de6feaa9822baad3f8e147e
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18493
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/451426
Add some generic functions that can configure the SPI interface to
have faster performance.
Given that the hudson files are used across many generations of FCHs,
make sure to refer to the appropriate BKDG or RRG before using the
functions. Notable differences:
* Hudson 1 defines read mode in CNTRL0 differently than later gens
* Hudson 1 supports setting NormSpeed in Cntr1 but Hudson3 allows
setting FastSpeed as well
* Kabini, Mullins, Carrizo and Stoney Ridge contain a "new" SPI100
controller
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 1922d6f424dcf1f42e2f21fb7c6d53d7bcc247d0)
BUG=none
BRANCH=none
TEST=none
Change-Id: Id65b4ca73e63657605c62ce79898328fb109ef79
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 91dea4a648
Original-Change-Id: Id12440e67bc575dbe4b980ef1da931d7bfae188d
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18442
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/451425
Add defines that will be used later for setting the fastest settings
in the SPI controller.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 0d2c28b8156dcc1f3dc925b3c3ba15b6b07f202c)
BUG=none
BRANCH=none
TEST=none
Change-Id: I79c2fea08731e9435c9f99930ad32e62bf39f6e1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7b0b9f0d41
Original-Change-Id: I660cc9ed6910c33042321c80453c7f74912455d9
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18441
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/451424
Remove unused definitions from a .c file and use the BIT(n) macro
found in types.h instead. Convert existing definitions to BIT(n).
Orignial-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit f403d12b49985ee9d9b339a6659b60ef1560519c)
BUG=none
BRANCH=none
TEST=none
Change-Id: I8a8cc49ed8496e4e429ce68d3a592d0380c49b60
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d8019a67bf
Original-Change-Id: I24105bf75263236dbdbc2666f03033069d1d36d2
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18440
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/451423
Fix the error detected by checkpatch and update the copyright date.
TEST=Build and run on Galileo Gen2
Change-Id: Ib425bc7672b5a2fd313b415bf2886c21c0ce0ce6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0de5b09104
Original-Change-Id: Idc55169913e7b7b0aca684c26f6ed3b349fc6c09
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18592
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/451422
Fix the errors detected by checkpatch and update the copyright dates.
TEST=Build and run on Galileo Gen2
Change-Id: I17cf98c093c6b89bf6216c0c566c5b7309483579
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 94b971a909
Original-Change-Id: Idad062eaeca20519394c2cd24d803c546d8e0ae0
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18591
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/451421
This was removed from the previous version, but we'd like it in
a separate patch, so it's obvious and can easily be applied to the
next version.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id1de5d6dac3a230804d03748346bcc35183f52d1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 93757f8543
Original-Change-Id: I9396009e82e762aa0cc037dbe9e7133962af6354
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18577
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/451362
This is version 03aed21 from linux/scripts, updated on Dec 12, 2016.
The version needs to be updated because Perl version 5.20 deprecated the
/C regex expression. Perl version 5.24 removed it completely, so the
old version fails to run on the coreboot builders.
BUG=none
BRANCH=none
TEST=none
Change-Id: I11ca194a4b8bb58433b3408006326f78217a6c71
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ae34e97ad7
Original-Change-Id: Ib97997237ca64c65d7f91d568ae4bec000804331
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/18571
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <f4bug@amsat.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/451361
Fix the following issues:
* A raw read is described by a single read segment, don't assert.
* Support reads longer than the FIFO size.
* Support writes longer than the FIFO size.
* Use the 400 KHz clock by default.
* Remove the error displays since vboot device polling generates
errors.
TEST=Build and run on Galileo Gen2
Change-Id: I0abfb0dd6247a089c7b0c5548dde6f509141f05a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 16568c7535
Original-Change-Id: I421ebb23989aa283b5182dcae4f8099c9ec16eee
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18029
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/451360
Configure the right GPIOs for finger print sensor interrupt and reset
lines.
As per the schematics GPP_C8 is for sensor interrupt and GPP_C9
is for sensor reset.
BUG=none
BRANCH=none
TEST=none
Change-Id: I0ef25ab9ca0f1215ea70d450bb7cff38ae4debb7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2ea12e5ce0
Original-Change-Id: Ib25c68ec2fe20b1302b6170d67ceab7e8cca1a83
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18389
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/451359
One very long line has to be wrapped to be shorter than 80 characters to
satisfy the lint scripts.
Note, that this gets rid of the brackets ().
BUG=none
BRANCH=none
TEST=none
Change-Id: I096cf6151a68e30a9b438d4b5526d72f0faacd94
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3329262eca
Original-Change-Id: Ie98eff360ebc5b68ce496edc15eb2d9fddcac868
Original-Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Original-Reviewed-on: https://review.coreboot.org/18556
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/451358
Status:
- The primary PCIe 16x slot works:
It was tested with a GPU compatible with nouveau
- USB and audio are not very reliable
- The ethernet card is not seen with lspci
- The secondary pcie16x slot isn't working:
When plugging a GPU inside, it's not seen with lspci
- SATA works: The board fully boots GNU/Linux
- Serial doesn't work
- Populating the RAM slots might have to follow
the recommended memory configuration that is described
in the mainboard manual in order to be able to boot.
Note that when running the shutdown command, the default
boot firmware will rewrite part of the boot flash before
powering off the machine.
Flashing coreboot internally from the default boot fimrware can
still work, if the power plug is removed after running flashrom.
BUG=none
BRANCH=none
TEST=none
Change-Id: I63e576c9e0b32a97b6575d2ef35448c22ad2889a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 420d3a93c1
Original-Change-Id: I934de521d0acceb7770f23b2ae15c31a67ae73eb
Original-Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Original-Reviewed-on: https://review.coreboot.org/16931
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/451272
These definitions do not require AGESA.h include,
and we will eventually remove agesawrapper.h files.
BUG=none
BRANCH=none
TEST=none
Change-Id: If0e0310f276c5d72fac69f959a935f0d4ac7aa76
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d610c5823c
Original-Change-Id: I1b5b78409828aaf2616e177bb54a054960c3869f
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18588
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/451271
The size of the array did not match that of the actual
allocation. Furthermore, the tables are written as
part of set_pci_irqs() in hudson/pci.c.
Also the removed code was never reached runtime, as it is
only executed on ACPI S3 resume path that is currently
disabled.
BUG=none
BRANCH=none
TEST=none
Change-Id: I39342e03eec9c71b2584bb078a6811193e302869
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 627d790651
Original-Change-Id: If1c47d53a7656bdff40d93fc132c8c057184ae46
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18587
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/451270
This file is only static defines.
BUG=none
BRANCH=none
TEST=none
Change-Id: I1518d84653ef98d3b00f9a43f48a656eb2e68afc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 50bb68f2b6
Original-Change-Id: Id50a0eba1ce240df36da9bd6b2f39a263fa613df
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18585
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Philippe Mathieu-Daud <f4bug@amsat.org>
Reviewed-on: https://chromium-review.googlesource.com/451268
The current elog implementation has two event types defined for 0xa7,
apparently the result of divergent coreboot trees on chromium where
some events were added to ARM systems but not upstreamed until later.
Fix this by moving ELOG_TYPE_THERM_TRIP to be 0xab, since the current
elog parsing code in chromium is using ELOG_TYPE_SLEEP for 0xa7.
BUG=b:35977516
TEST=check for proper "CPU Thermal Trip" event when investigating a
device that is unexpectedly powering down.
Change-Id: I3dbba826383f9dd911f910d8f9e6db7433463a10
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6cbd3980ab
Original-Change-Id: Idfa9b2322527803097f4f19f7930ccbdf2eccf35
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18579
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/451264
Move all common MSRs as per IA SDM into a common location
to avoid duplication.
BUG=none
BRANCH=none
TEST=none
Change-Id: Idfb8d874d83e38c112a07bea24909b6493717cfd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c2fd0a2114
Original-Change-Id: I06d609e722f4285c39ae4fd4ca6e1c562dd6f901
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18509
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/451261
It seems that we should only ever run at 900mV on center logic.
Changing it to 950mV before might have just masked over problems that
are now fixed.
BRANCH=none
BUG=chrome-os-partner:56940
TEST=on kevin, run
stressapptest -M 1536 -s 1000
Change-Id: I5a09b1b403df800396bb2f2e8c76d14a4519d44a
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/388068
Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Tested-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Lin Huang <hl@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
