Commit graph

882 commits

Author SHA1 Message Date
Peter Stuge
84c6bce2c6 Fix device name in ac97audio dts.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@882 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-03 04:08:15 +00:00
Ronald G. Minnich
d3ae8e7951 Let's add sb600 to the v3 repo this time.
My apologies. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@881 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-03 03:56:56 +00:00
Ronald G. Minnich
e4e80a7ee0 add new socket type (trivial)
Signed-off-by: Ronald G. Minnich <rminnch@gmail.com>
Acked-by: Ronald G. Minnich <rminnch@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@880 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-02 16:07:10 +00:00
Uwe Hermann
8e6d45e059 Minor fixes and improvements for v3, mostly for Kconfig files (trivial).
- Coding style and whitespace fixes.
 - Remove obsolete comments, fix incorrect ones.
 - Use the full/canonical name of mainboards/vendors everywhere.
 - Update the list of USB Debug capable chipsets from
   http://www.coreboot.org/EHCI_Debug_Port.
 - s/LB/CB/ for the CONSOLE_PREFIX kconfig option.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@879 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-01 18:29:22 +00:00
Uwe Hermann
42e98f5d49 Coding style and documentation fixes for AMP TinyGX (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@878 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-01 17:54:56 +00:00
Ronald G. Minnich
11c6d0d98d m57sli mostly builds again. The stage0 is too large at 24k.
We need to figure out if we should just grow stage0. My inclination is 
to say 'yes'.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@877 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-01 07:23:05 +00:00
Ronald G. Minnich
76167990ed Bringing the m57sli to life. This includes changes to mcp55 and
mainboard that we learned with the serengeti that we needed. New 
function in pnp that is for reading. new prototype in pnp.h. New 
constants for ite8716f. 

This board does not build yet; we are exercising code in k8 north that
the serengeti did not enable. More tomorrow. 

Now that we have two boards under way we can hopefully see our way to 
getting more put in. The 690 is the obvious next choice. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@876 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-01 06:47:51 +00:00
Jordan Crouse
eea8cca061 The defconfig should not have a payload specified to play nice
with buildrom.  Informally acked by Ron.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@875 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-29 17:24:44 +00:00
Ronald G. Minnich
7f0c577dc2 defconfig for buildrom
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@874 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-29 15:42:25 +00:00
Ronald G. Minnich
6d38e04683 quick emergency fix for gnu tools that now have elaborate note names
such as .note.this.that. These new note names were making builds 
unbuildable on (e.g.) fc9.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@873 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-29 15:37:26 +00:00
Ronald G. Minnich
be03d189db Finally, after two years, put in real code for stop_ap(). Code has to be
moved to stage1 ROM code. Make the struct for nodeid/coreid generic to 
x86. Create the functions for existing architectures are a model for 
future architectures (VIA coming soon we hope). 

Move includes so that things build correctly now. 

This is actually a small patch that impacted a number of files due to 
include order changes. This is build and boot tested on simnow and 
build tested on geode. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@872 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-29 14:58:56 +00:00
Ronald G. Minnich
216231c0de Forgot to add this one.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@871 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-29 05:14:55 +00:00
Jordan Crouse
f9dc3f1528 Signed-off-by: Robert Millan <rmh@aybabtu.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@870 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-24 14:54:33 +00:00
Ronald G. Minnich
f2c21f5827 Continue cleanup. Still boots to etherboot in simnow.
Far fewer warnings than before :-)

TODO: Document the DIMM_SETTINGS variable. 
FIx up fidvid code. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@869 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-19 20:00:17 +00:00
Ronald G. Minnich
e053a1004c substantial cleanups for k8.
AMP TinyGX still builds, this won't affect other platforms. 

clean up 8111 stage1 code; add function to smbus, 
memreset_setup_amd8111, for the 8111 specific parts of memreset. 

include k8 .h to reduce warnings. Turn some things into functions (romcc
legacy cleanup) and put them in .c files. 

simnow actually successfully gets through a reset cycle now. 

Next is to fix the fidvid code. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@868 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-19 18:35:22 +00:00
Ronald G. Minnich
7ea90e1809 This set of changes adds new nodes to dts that are required, adds
some prints, and fixes a null pointer deref bug that has been in the 
k8 code since the dawn of time. 

We get here: 

CPU 804 Mhz
Etherboot 5.4.3 (GPL) http://etherboot.org
Drivers: VIA-VELOCITY/PCI   Images: ELF   
Protocols: DHCP TFTP 
Relocating _text from: [000100e0,000349c0) to [0007b720,000a0000)
Boot from (N)etwork or (Q)uit? 

Probing pci nic...
Probing isa nic...
<sleep>

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@867 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-18 16:45:46 +00:00
Ronald G. Minnich
31bae795c4 Accidental commit -- this is a local change i have to have for my broken dbe62,
and I committed it by accident.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@866 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-17 16:38:16 +00:00
Ronald G. Minnich
28ecbeab88 The K8 is one example, but there are other devices (e.g. I2C) that also have
multiple links. The way this was done in v2 was a big confusing; this way is 
less so. 

The changes are easy. Getting them right has been hard :-)

First, for a k8 north that has three links, you can name each one as follows:
pci0@18,0
pci1@18,0
pci2@18,0

We have to have the same pcidevfn on these because that is how the k8 works. 
But the unit numbers (pci0, pci1, etc.) distinguish them. 

The dts will properly generate a "v3 device code" 
compatible static tree that puts the links in the right place in the 
data structure. 

The changes to dts are trivial. 
As before, dts nodes with children are understood to be a bridge. 
But what if there is a dts entry like this:
pci1@18,0 {/config/("northbridge/amd/k8/pci");};


This entry has no children in the dts. 
How does dt compiler know it is a bridge? It can not know unless 
we add information to the dts for that northbridge part. 
To ensure that all bridge devices are detected, we support the following: 
if a dts node for a device has a bridge property, e.g.: 
 {
        device_operations = "k8_ops";
       bridge;
 };

The dt compiler will treat it as a bridge whether it has children or not. 

Why would a device not have children? Because it might be attached to a
pci or other socket, and we don't know at build time if the socket is empty, 
or what might be in the socket. 

This code has been tested on dbe62 and k8 simnow, and works on each. 
It is minimal in size and it does what we need. I hope it resolves our 
discussion for now. We might want to improve or change the device code
later but, at this point, forward motion is important -- I'm on a deadline for
a very important demo Oct. 22!

Also included in this patch are new debug prints in k8 north. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@865 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-17 16:36:20 +00:00
Ronald G. Minnich
d7ef3c4fd2 EMERGENCY patch for a stupid typo. This code won't compile without these includes.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@864 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-17 16:29:02 +00:00
Ronald G. Minnich
5a74d7889b Here is an alternate approach to getting rid of the static in cs5536
smbus.

Set up a global var variable called spd_inited. It is set when spd is 
inited.

For simple cases, nothing is visible to initram main. For complex cases,
initram main can do the work and set this variable.

This compiles and runs on dbe62, which is actually meaningless since 
dbe62
has not smbus, but hey ...

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@863 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-17 02:19:59 +00:00
Ronald G. Minnich
74e0a0a268 Make debug conditional.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@862 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-16 03:21:29 +00:00
Uwe Hermann
79f52eb97b Port some of the recent SPD DDR2 #defines from v2 to v3 (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@861 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-07 17:18:10 +00:00
Carl-Daniel Hailfinger
c2084e9de3 I managed to break dtc while working on PCI bridges:
dtc only uses dev_fn as identifier for a PCI device. That gets us a name
collision if we have the same dev_fn combination on multiple buses.
Either we add a random unique ID to the struct name or we integrate the
path to the parent device as well.
I decided to go for integration of parent device path.

With the following device tree

/{
        cpus {};
        domain@0 {
                bus@0 {
                        pci@0,0 {
                        };
                        pci@1,1 {
                        };
                        pci@f,0 {
                                bus@1 {
                                        pci@0,0 {
                                        };
                                };
                        };
                };
        };
};


we get the old names:
dev_root
dev_cpus
dev_domain_0
dev_bus_0
dev_pci_0_0
dev_pci_1_1
dev_pci_f_0
dev_bus_1
dev_pci_0_0 COLLISION!!!

and the new names:
dev_root
dev_cpus
dev_domain_0
dev_domain_0_bus_0
dev_domain_0_bus_0_pci_0_0
dev_domain_0_bus_0_pci_1_1
dev_domain_0_bus_0_pci_f_0
dev_domain_0_bus_0_pci_f_0_bus_1
dev_domain_0_bus_0_pci_f_0_bus_1_pci_0_0

Ron would like shorter names because they only have to be
machine-readable. That's left for another patch.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@860 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-06 20:39:25 +00:00
Carl-Daniel Hailfinger
d2d95b25cc The .next pointer was written twice for every struct device in
statictree.c. This bug was introduced in r175.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@859 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-06 20:30:26 +00:00
Carl-Daniel Hailfinger
ade1cd1f11 The current K8 stack preservation code in disable_car() works by chance,
but that's not something we should rely on.

The new code is entirely rewritten, fixes a few missing constraints in
the asm and should be a lot more readable. However, the generated code
is NOT identical. The old code was broken because of the missing ecx
clobber constraint and it did not copy the stack back (ecx was zero at
the beginning of the copy-back loop and so the loop executed exactly
zero times).
So this is a genuine bug fix.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Ron writes:
wow! nice catch!

Acked-by: Ronald G. Minnich <rminnich@gmail.com>

We also need disable_car_and_halt, which only disables car and halts,
for the APs (i.e. no need to copy stack back)


git-svn-id: svn://coreboot.org/repository/coreboot-v3@858 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-05 10:29:33 +00:00
Carl-Daniel Hailfinger
49e1879723 Fix initial printk buffer address initialization. This was broken in
r785 (move from explicit asm to implicit C) and unfortunately qemu never
triggered the bug, only real hardware did. That's because qemu will not
spew an error on access to RAM before RAM is enabled.

Thanks to Ron for bisecting this.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@857 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-04 15:35:49 +00:00
Carl-Daniel Hailfinger
f9b114054c Improve debugging printks for LAR and PCI access.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@856 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-04 00:38:54 +00:00
Ronald G. Minnich
72be710b4b With this change, we get all the way to stage 2 and this output, at
which point we hang:
Show all devs...
root(Root Device): enabled 1 have_resources 0 initialized 0
cpus: Unknown device path type: 0
cpus(): enabled 1 have_resources 0 initialized 0
apic_0(APIC: 00): enabled 1 have_resources 0 initialized 0
pci_1_0(PCI: 00:01.0): enabled 1 have_resources 0 initialized 0
pci_0_0(PCI: 00:00.0): enabled 1 have_resources 0 initialized 0
pci_4_0(PCI: 00:04.0): enabled 1 have_resources 0 initialized 0
pci_5_0(PCI: 00:05.0): enabled 1 have_resources 0 initialized 0
pci_18_0(PCI: 00:18.0): enabled 1 have_resources 0 initialized 0
ioport_2e(IOPORT: 2e): enabled 1 have_resources 0 initialized 0
domain_0(PCI_DOMAIN: 0000): enabled 1 have_resources 0 initialized 0
Phase 6: Initializing devices...
Phase 6: Root Device init.
Phase 6: PCI: 00:04.0 init.

The dts is quite incomplete and that is part of the problem. Doubtless 
there are other problems :-)

But training is indeed working in simnow, and memory is working, and we 
can return from disable_car as on the geode. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@855 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-02 15:25:06 +00:00
Ronald G. Minnich
9cdd8a9d67 This finishes the fix to log2. The computed dram size now matches the
size indicated by byte 31 of SPD. 

Memory is still not working; hanging in dqs training. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@854 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-01 02:44:08 +00:00
Ronald G. Minnich
c24361eba7 remaining fixes for log2. Simple prototype added to spd_ddr2.h
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@853 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-31 20:39:48 +00:00
Ronald G. Minnich
3b384ce2a2 log2 is now log2f (floor) and log2c (ceiling) and users MUST pick one or
the other. It really matters for non-power-of-2 numbers. 

This breaks k8 builds; fix is coming. 
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@852 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-31 20:28:21 +00:00
Ronald G. Minnich
47043d7ab3 add some printks to raminit and correct a typo on one comment.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@851 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-31 02:46:37 +00:00
Ronald G. Minnich
4aebc1be66 Fix a really stupid error on my part :-)
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@850 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-30 05:01:43 +00:00
Ronald G. Minnich
5f1864114d Hacks to get us trying to read the smbus.
There is really strange logic in the init_cpus, and it needs cleanup. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@849 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-30 04:20:03 +00:00
Ronald G. Minnich
df00b48496 One typo and one change to get our bootblock back into 20k.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@848 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-30 03:42:01 +00:00
Ronald G. Minnich
ff2ddcb313 This gets us back to a compiling k8 target.
This code has been tested on dbe62, and builds for qemu as well. 

the next step is testing on simnow. 

k8.h: add more prototypes and some required inline functions. 
cpu.h: same
serengeti: expand defines in mainboard.h, though we need a better 
mechanism; continue to fix initram.c, add new support files to Makefile
lib/console.c: include globalvars.h
lib/lar.c: Provide more informative print as the lar is scanned.
k8 north: needed reset_test.c from v2, fixes to raminit.c
arch/x86
Kconfig: new CONFIG variable CBMEMK, meaning coreboot mem k, memory
	used for coreboot. 
init_cpus.c: functions to start up CPUs
stage1_mtrr.c: bring over early mtrr support from v2.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@847 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-30 03:35:40 +00:00
Carl-Daniel Hailfinger
6fd4e56dd7 Remove SUPERIO_WINBOND_W83627HF from Qemu Kconfig. Qemu does not have an
external Super I/O.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@846 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-29 21:18:09 +00:00
Carl-Daniel Hailfinger
a3dd66b628 Improve pci scan debugging. This helped me find a rather nasty bug.
Message level is BIOS_SPEW for everything except error conditions.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@845 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-29 09:06:13 +00:00
Carl-Daniel Hailfinger
5e4770fc02 Prepare for per-device subsystem IDs.
Fix the bus location for Qemu IDE.

This patch only provides the needed infrastructure for per-device
subsystem IDs, it does not hook them up to the PCI core yet, so this
patch is a no-op.
By the way, the on_mainboard property is activating lots of completely
untested code paths in v3, so someone might want to audit them.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@844 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-29 08:49:24 +00:00
Ronald G. Minnich
f365719d09 This is closer! There are < 10 functions to be worked out, so most of
what you get are warnings. 

There is lots of room for improvement as we move to all CAR 
code, but that will take time. 

I hope to get this to really compile over the weekend. 

At the same time, if anybody wants to take a crack at it, your efforts
are welcome.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@843 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-29 04:33:56 +00:00
Stefan Reinauer
87adbc377b small dependency fix, plus make oldconfig & co need libintl, too :)
(trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@842 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-28 22:44:49 +00:00
Ronald G. Minnich
fd31dee2a6 Closer to compiling. Add the fidvid functions. Continue to remove romcc
legacy. Use constants as much as possible instead of magic numbers. Set 
up common prototypes in an include file. 

The fidvid needs major cleanup but this code is so tricky I don't want 
to start cleanup until I feel it is more or less working. 

Signed-off-by: Ronald G. minnich <rminnich@gmail.com>
Acked-by: Ronald G. minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@841 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-28 17:14:04 +00:00
Stefan Reinauer
acf7535747 fix typo
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@840 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-28 07:15:43 +00:00
Ronald G. Minnich
6fd7abea43 Off to bed. I'm done for now.
If anyone wants to review my comments, or maybe even try to fix compile 
issues, have at it :-)

The more I work with the K8 stuff the more impressed I am with the 
people who got it all to go 6 years ago. (and at how much I've forgotten 
but that's another story :=)

If we can get this next step done we're very close to having a working 
initram. 

And, once you have ram and hit stage2, life is just better all around.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@839 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-28 05:41:48 +00:00
Carl-Daniel Hailfinger
08f7cd8688 stage1_main() calling conventions changed to use two parameters instead
of one. This resulted in a stack underflow for i586 and GeodeLX because
the stack was set up for only one parameter in their stage0 asm code.

Untested. Note that this didn't trigger on K8 because the stack setup
there has excessive room, something that should be fixed as well.

This is a band-aid and we should do it right instead. Discussion
follows:

Carl-Daniel Hailfinger wrote:
> Can't we determine init_detected from C code and avoid working with it
> in asm?
> The Fam10h BKDG states in section 2.3.1:
> "determine the type of this reset. One method is to use [The Link
> Initialization Control Register] F0x6C[InitDet] bit."
> The same register is suggested by the Athlon64/Operon BKDG and the
> Fam0fh BKDG.
> 
> That should work from C and make our lives easier. To be honest, I
> have no idea why we use bit 11 of MTRRdefType_MSR for the
> init_detected purpose.

Ron Minnich wrote:
> I plan to change that in future. For now, I want to change as little
> as I can, since this code is so mysterious anyway. I would say let's
> leave it in with a warning of some sort.


Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@838 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-28 02:55:14 +00:00
Ronald G. Minnich
d130a25c0d This code is not in a working state but I want to get it into the repo
since the box it is on is kinda old. 

I realize it is wrong but it is getting there. 

The k8 startup is a work of genius. I hope at some point it will be a 
work of genius that the rest of us can understand :-)

But it's very impressive code in how it works.

Discussions with AMD: we're in agreement that the structure of this code 
will change for the better, but it's helpful to have this audit trail of 
changes.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@837 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-28 02:37:29 +00:00
Ronald G. Minnich
b0144f19c7 This code is not in a working state but I want to get it into the repo
since the box it is on is kinda old. 

I realize it is wrong but it is getting there. 

The k8 startup is a work of genius. I hope at some point it will be a 
work of genius that the rest of us can understand :-)

But it's very impressive code in how it works.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@836 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-28 02:35:56 +00:00
Ronald G. Minnich
b4117a2dc3 Fix for globals for qemu.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@835 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-28 02:32:27 +00:00
Carl-Daniel Hailfinger
3e9b43f32f BIST handling. Unless I'm mistaken, we already die() in stage1_main() if
processor BIST is nonzero. Checking it in initram makes no sense. Having
it as global variable is unnecessary as well. Link BIST is an entirely
different animal.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@834 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-28 01:57:14 +00:00
Carl-Daniel Hailfinger
4af8efa416 Documentation improvement for sys_info.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@833 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-28 01:31:24 +00:00