The word 'coreboot' should always be written in lowercase, even at the
start of a sentence.
BUG=none
BRANCH=none
TEST=none
Change-Id: I280a7abeada01b4d158b2d65c3b59f1b98b81ad9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e18e6427d0
Original-Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2
Original-Signed-off-by: Martin Roth <martinroth@google.com>
Original-Reviewed-on: https://review.coreboot.org/20029
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/528259
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
from FSP release V030_61
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibc2f9d7a51c8428b95de74a672b36c1f2572fb5e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 0435f97acb
Original-Change-Id: I5ecba08de851ee2e362f9ac31e1fa8bf3dfceebb
Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19605
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/506211
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
The AP sends the Cr50 a request to enable the new firmware image. If
the new Cr50 image was found and enabled, the AP expects the Cr50 to
reset the device in 1 second.
While waiting for the Cr50 to reset, the AP logs a newly defined event
and optionally shuts down the system. By default the x86 systems power
off as shutting those systems down is not board specific.
BRANCH=gru,reef
BUG=b:35580805
TEST=built a reef image, observed that in case cr50 image is updated,
after the next reboot the AP stops booting before loading depthcharge,
reports upcoming reset and waits for it.
Once the system is booted after that, the new event can be found
in the log:
localhost ~ # mosys eventlog list
...
7 | 2017-03-23 18:42:12 | Chrome OS Developer Mode
8 | 2017-03-23 18:42:13 | Unknown | 0xac
9 | 2017-03-23 18:42:21 | System boot | 46
...
Change-Id: I12706aebb64d6fb6b53386d8e9379b5781a7a84e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b9126fe46c
Original-Change-Id: I45fd6058c03f32ff8edccd56ca2aa5359d9b21b1
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18946
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/498315
The CR50 TPM can do both SPI and I2C communication. However,
there's situations where policy needs to be applied for CR50
generically regardless of the I/O transport. Therefore add
MAINBOARD_HAS_TPM_CR50 to encompass that. Additionally,
once the mainboard has selected CR50 TPM automatically select
MAINBOARD_HAS_TPM2 since CR50 TPM is TPM 2.0.
Change-Id: I878f9b9dc99cfb0252d6fef7fc020fa3d391fcec
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19370
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/482741
Commit-Ready: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Bottom five LSBs are used to store the running frequency
of memory clock.
BUG=none
BRANCH=none
TEST=none
Change-Id: If241c224ecb5b5aed3e308d126cd1d7d0314417e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e522258907
Original-Change-Id: I2dfcf1950883836499ea2ca95f9eb72ccdfb979c
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19042
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/472718
Add package options to the CPU Kconfig that may be selected by the
mainboard's Kconfig file. Stoney Ridge is available in FP4 and FT4
packages and each requires a unique binaryPI image. Default to the
correct blob used by the northbridge by looking at the CPU's package.
Also modify Gardenia to select the right package.
See the Infrastructure Roadmap for FP4 (#53555) and FT4 (#55349) for
additional details for the packages.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 7b8ed7b732b7cf5503862c5edc6537d672109aec)
BUG=none
BRANCH=none
TEST=none
Change-Id: I2fcb523d6cfef530fb7b2a9b9c7ca2e92a73297f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5995ee62f7
Original-Change-Id: I7bb15bc4c85c5b4d3d5a6c926c4bc346a282ef27
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18989
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/471465
Memory training data that is saved as part of S3 feature in SPI
flash can be used to bypass training on normal boot path as well.
When RegisterSize is 3 in the register playback tables, no register is
saved or restored. Instead a function is called to do certain things in
the save and resume sequence. Previously, this was overlooked, and the
pointer containing the current OrMask was still incremented by 3 bytes.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ifeca0a8ab69209a4ce9c78cbdc97c82563a5f5ee
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c91ab1cfce
Original-Change-Id: I7221a03d5a4e442817911ba4862e3c0e8fa4a500
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19041
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/471462
This patch attempts to finish the separation between CONFIG_VBOOT and
CONFIG_CHROMEOS by moving the remaining options and code (including
image generation code for things like FWID and GBB flags, which are
intrinsic to vboot itself) from src/vendorcode/google/chromeos to
src/vboot. Also taking this opportunity to namespace all VBOOT Kconfig
options, and clean up menuconfig visibility for them (i.e. some options
were visible even though they were tied to the hardware while others
were invisible even though it might make sense to change them).
CQ-DEPEND=CL:459088
Change-Id: I45230f7a73521d66fdc46a54ee9bde32b3e7eae7
Original-Change-Id: I3e2e31150ebf5a96b6fe507ebeb53a41ecf88122
Original-Reviewed-on: https://review.coreboot.org/18984
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Id: 58c3938705
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/462014
This callback was only required for a single mainboard, and it can
easily be moved to mainboard-specific code. This patch removes it from
the global namespace and isolates it to the Jecht board. (This makes
it easier to separate vboot and chromeos code in a later patch.)
Change-Id: Ida287e5b48f4543b9caee1a81c302044bd041edc
Original-Change-Id: I9cf67a75a052d1c86eda0393b6a9fbbe255fedf8
Original-Reviewed-on: https://review.coreboot.org/18981
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Original-Commit-Id: b04cc6b902
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/462011
The virtualized developer switch was invented five years ago and has
been used on every vboot system ever since. We shouldn't need to specify
it again and again for every new board. This patch flips the Kconfig
logic around and replaces CONFIG_VIRTUAL_DEV_SWITCH with
CONFIG_PHYSICAL_DEV_SWITCH, so that only a few ancient boards need to
set it and it fits better with CONFIG_PHYSICAL_REC_SWITCH. (Also set the
latter for Lumpy which seems to have been omitted incorrectly, and hide
it from menuconfig since it's a hardware parameter that shouldn't be
configurable.)
Since almost all our developer switches are virtual, it doesn't make
sense for every board to pass a non-existent or non-functional developer
mode switch in the coreboot tables, so let's get rid of that. It's also
dangerously confusing for many boards to define a get_developer_mode()
function that reads an actual pin (often from a debug header) which will
not be honored by coreboot because CONFIG_PHYSICAL_DEV_SWITCH isn't set.
Therefore, this patch removes all those non-functional instances of that
function. In the future, either the board has a physical dev switch and
must define it, or it doesn't and must not.
In a similar sense (and since I'm touching so many board configs
anyway), it's annoying that we have to keep selecting EC_SOFTWARE_SYNC.
Instead, it should just be assumed by default whenever a Chrome EC is
present in the system. This way, it can also still be overridden by
menuconfig.
CQ-DEPEND=CL:459701
Change-Id: I33d6fe4570b6c7e6d120ed43736413ace0016454
Original-Change-Id: If9cbaa7df530580a97f00ef238e3d9a8a86a4a7f
Original-Reviewed-on: https://review.coreboot.org/18980
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Id: 320edbe2ba
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/462010
The correct way to mock out vboot TPM accesses these days is the
CONFIG_VBOOT_MOCK_SECDATA Kconfig option. There are some remnants of
older TPM-mocking infrastructure in our codebase that are as far as I
can tell inert. Remove them.
Change-Id: I62e2c58a2d8796f43690ca3525074caa4977bde1
Original-Change-Id: I3e00c94b71d53676e6c796e0bec0f3db67c78e34
Original-Reviewed-on: https://review.coreboot.org/18977
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Commit-Id: 84b2978ed6
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/462006
cr50 by default delays nvmem commits internally from the point of
reset to accumulate change state. However, the factory process can
put a board into dev mode through the recovery screen. This state
is stored in the TPM's nvmem space. When the factory process is
complete a disable_dev_request and battery_cutoff_request is performed.
This leads to disabling the dev mode in TPM, but the battery is
subsequently cut off so the nvmem contents never stick. Therefore,
whenever antirollback_write_space_firmware() is called we know there
was a change in secdata so request cr50 to immediately enable nvmem
commits going forward. This allows state changes to happen immediately.
The fallout from this is that when secdata is changed that current
boot will take longer because every transaction that writes to TPM
nvmem space will perform a write synchronously. All subsequent boots
do not have that effect.
It should also be noted that this approach to the implementation is
a pretty severe layering violation. However, the current TPM APIs
don't lend themselves well to extending commands or re-using code
outside of the current routines which inherently assume all knowledge
of every command (in conflict with vendor commands since those are
vendor-specific by definition).
BUG=b:35775104
BRANCH=reef
TEST=Confirmed disablement of dev mode sticks in the presence of:
crossystem disable_dev_request=1; crossystem
battery_cutoff_request=1; reboot;
Change-Id: Ia2f5ec97f750570c3b16aa68b01ab1eaa94f6960
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: eeb77379e0
Original-Change-Id: I3395db9cbdfea45da1f5cb994c6570978593b944
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18681
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452888
In all simplicity, with board/OptionsIds.h file having:
IDSOPT_IDS_ENABLED TRUE
IDSOPT_TRACING_ENABLED TRUE
And src/Kconfig modified to:
config WARNINGS_ARE_ERRORS
default n
With these settings AGESA outputs complete debugging log
where-ever you have your coreboot console configured.
BUG=none
BRANCH=none
TEST=none
Change-Id: Id2a2b54b1aa2d2ad497b2fa25f418c52244c3fb3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 86ee4db0d8
Original-Change-Id: Ie5c0de6358b294160f9bf0a202161722f88059c1
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15320
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452470
We have been forced to build AGESA with ASSERT() as non-fatal
for some board, as hitting those errors is not uncommon.
For the cases touched here, abort eventlog operations early
to avoid further errors and dereference of null pointers.
BUG=none
BRANCH=none
TEST=none
Change-Id: I342e3195585ca435749886e990b40ea65e2bd311
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bfa72ce23b
Original-Change-Id: I1a09ad55d998502ad19273cfcd8d6588d85d5e0c
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18543
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/452468
Implement threshold as described in AMD.h, and do not add
entries below STATUS_LOG_LEVEL in the eventlog.
BUG=none
BRANCH=none
TEST=none
Change-Id: I41a257d8482bdeb568689045511547484c33e3c0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4f74c89592
Original-Change-Id: Ic9e45b1473b4fee46a1ad52d439e8682d961dc03
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18542
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/452466
The event log entry indicating developer mode is useful for the
boot path, but is not really useful on the resume path and removing
it makes the event log easier to read when developer mode is enabled.
To make this work I have to use #ifdef around the ACPI code since
this is shared with ARM which does not have acpi.h.
BUG=b:36042662
BRANCH=none
TEST=perform suspend/resume on Eve and check that the event log
does not have an entry for Chrome OS Developer Mode.
Change-Id: Ief6dead73856689f0fb0bce6266d66c7196340ee
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f8401cddb8
Original-Change-Id: I1a9d775d18e794b41c3d701e5211c238a888501a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18665
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452361
Add the MemInfoHob.h provided by FSP v1.6.0 for aid in parsing the
MEM_INFO_DATA_HOB.
BUG=chrome-os-partner:61729
BRANCH=none
TEST=Build and boot KBLRVP
Change-Id: I0f6d691fcc4c3be900108dda8fb1d8cc7d3c3144
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9e54978f6e
Original-Change-Id: Ia2b528ba4d9f093006cc12ee317d02e7f3e83166
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18326
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/449820
The FSP UPD offsets and the corresponding structure size do not match,
CpuConfigData.h needs an update to align the same. Hence update the
header file based on FSP version 1.4.0.
BUG=chrome-os-partner:61548
BRANCH=none
TEST=Built and booted KBLRVP and verify that all UPDs are in sync in
both coreboot and FSP.
Change-Id: I817c13aaac891f5aef075ba66d8d66aba2346f97
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6ff7e8f550
Original-Change-Id: I5ef7cbb569c3d1a44e7846717201952a0acf12ab
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18285
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/440166
These updated header files contain USB tuning parameters as well as
some general cleanup of unused parameters in the UPD Headers. This
patch along with the upcoming FSP 1.3.0 release will allow for USB
tuning on apollolake platforms.
CQ-DEPEND=CL:*315403
BUG=chrome-os-partner:61031
Change-Id: Icfd57b5358e5598618d7a91af6ba74baddee2fc0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e7056a82e0
Original-Change-Id: Id7cce1ea83057630d508523ada18c5425804535e
Original-Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18046
Original-Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/427764
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
On Chrome OS devices that use TPM2 parts the platform hierarchy
is disabled by the boot loader, depthcharge. Since the bootloader
isn't involved in resuming a suspended machine there's no equivalent
action in coreboot to disable the platform hierarchy. Therefore, to
ensure consistent state in resume the platform hierarchy in the TPM2
needs to be disabled as well. For systems that resume using the
firmware the platform hierarchy is disabled when utilizing
TPM2 devices.
BUG=chrome-os-partner:61097
BRANCH=reef
TEST=Suspend and resume. Confirmed 'stop trunksd; tpmc getvf; start
trunksd' shows that phEnable is 0.
Change-Id: I144a36d8ff10ce92d3de0b26d924fd85468a9764
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f56c7787ba
Original-Change-Id: I060252f338c8fd68389273224ee58caa99881de8
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18096
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428254
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Build issues were somehow overlooked in commit
ed840023a8:
1. hexstrtobin is not defined (needs the lib.h);
2. coreboot default compiler doesn't like variable initialization
within for loop.
BUG=chrome-os-partner:60821
TEST=Build and boot lars and reef
Change-Id: Iaf8ccf86e3b53fac481f28356d838728149d3e49
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id:
Original-Change-Id: I85b1394956ceb9b64e1b72f9f71982b6205d5a99
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Original-Commit-Id: feb4ef6d92
Original-Original-Change-Id: Ie52c1f93eee7d739b8aaf59604875f179dff60d0
Original-Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Original-Reviewed-on: https://review.coreboot.org/18076
Original-Original-Tested-by: build bot (Jenkins)
Original-Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428251
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
A VPD entry "wifi_sar" needs to be created which contains a heximal
encoded string in length of 40 bytes. get_wifi_sar_limits() function
retrieves and decodes the data from the VPD entry, which would later
be consumed by platform code.
BUG=chrome-os-partner:60821
TEST=Build and boot lars and reef
Change-Id: I73333bef1fec2769f4edb52c3e1f7262070ec5df
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ed840023a8
Original-Change-Id: I923b58a63dc1f8a7fdd685cf1c618b2fdf4e7061
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://review.coreboot.org/17958
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/427465
In the factory it's helpful for knowing when a system being
built is meant for release with all the security features
locked down. Provide support for exporting this type of pin
in the acpi tables.
BUG=chrome-os-partner:59951
BRANCH=reef
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17802
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Iec70249f19fc36e5c9c3a05b1395f84a3bcda9d0
Reviewed-on: https://chromium-review.googlesource.com/420830
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
BUG=chromium:595715
BRANCH=none
TEST=/build/$board/firmware/coreboot.rom has a zeroed out SHARED_DATA
region if it exists.
Change-Id: I0b59f1f0e2f8645000f83cb3ca7f49e4da726341
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/417821
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Chrome OS images have three firmware ID regions, to store version
information for the read-only and the two read-write areas. Fill them
with a suitable default and allow configuring a different scheme.
There's already an override in google/foster and google/rotor to match
the naming scheme used so far (in depthcharge).
BUG=chromium:595715
BRANCH=none
TEST=/build/$board/firmware/coreboot.rom has the expected values in the
regions.
Change-Id: I2fa2d51eacd832db6864fb67b6481b4d27889f52
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/417320
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
While searching for a field in all blocks ensure that the checked block
is available and can be used. In this way a field can be retrieved from
every block and not just the first one.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/17670
Tested-by: build bot (Jenkins)
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Change-Id: Idbd7656ab0664763cb065f5e817193ad1d9e0871
Reviewed-on: https://chromium-review.googlesource.com/417091
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the location of HWID field so that hwilib supports this
value as well.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/17575
Tested-by: build bot (Jenkins)
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Change-Id: If6d4695f861232231ac8f9c247c0a10410dac1c5
Reviewed-on: https://chromium-review.googlesource.com/415076
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When IDSOPT_TRACING_ENABLED is TRUE build fails with
"cast from pointer to integer of different size"
Use "UINTN" as is done in Family 16h.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: ukasz Dobrowolski <lukasz@dobrowolski.io>
Reviewed-on: https://review.coreboot.org/17406
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Change-Id: I362e67fc83aa609155f959535f33be9c150c7636
Reviewed-on: https://chromium-review.googlesource.com/415058
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of defining the same functions for reading/clearing boot-mode
switches from EC in every mainboard, add a common infrastructure to
enable common functions for handling boot-mode switches if
GOOGLE_CHROMEEC is being used.
Only boards that were not moved to this new infrastructure are those
that do not use GOOGLE_CHROMEEC or which rely on some mainboard specific
mechanism for reading boot-mode switches.
BUG=None
BRANCH=None
TEST=abuild compiles all boards successfully with and without ChromeOS
option.
Change-Id: I267aadea9e616464563df04b51a668b877f0d578
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17449
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/412854
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Provide an option to deliver the mainboard smbios version in the
form of 'rev%d' based on the board_id() value.
BUG=chromium:663243
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17290
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Change-Id: If0a34935f570612da6e0c950fd7e8f0d92b6984f
Reviewed-on: https://chromium-review.googlesource.com/410074
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Make changes to the vendorcode files that allow them to work
with the binaryPI. This fixes various compile issues and
establishes a common calling convention between coreboot and
AGESA.
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry picked from commit f7ea2785d70bd6813b5b4d315b064802251d9557)
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17195
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: Ie36228476a9dbd7b83f95828ca9c7252cecd8ec8
Reviewed-on: https://chromium-review.googlesource.com/408967
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Make exact copies of the AGESA files from the Stoney PI package
replacing existing versions. Change the license text and fix
up misc. whitespace.
This will facilitate the review of binaryPI changes in the
vendorcode directory.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 1097249585ab76fab59dcfbf8e7a419f34fcfcb6)
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17194
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I9951df58aeab2d533efc0a837ce35f343ff28d7c
Reviewed-on: https://chromium-review.googlesource.com/408966
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These header files contain a few new UPDs. The EnableS3Heci2
UPD will be used to save ~100ms from the S3 resume time on
Apollolake chrome platforms.
BUG=chrome-os-partner:58121
BRANCH=none
TEST=built coreboot for reef and verified no regressions
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/16869
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I1f324d00237c7150697800258a2f7b7eed856417
Reviewed-on: https://chromium-review.googlesource.com/396165
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Kconfig hex values don't need to be in quotes, and should start with
'0x'. If the default value isn't set this way, Kconfig will add the
0x to the start, and the entry can be added unnecessarily to the
defconfig since it's "different" than what was set by the default.
A check for this has been added to the Kconfig lint tool.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16834
Tested-by: build bot (Jenkins)
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Change-Id: I86f37340682771700011b6285e4b4af41b7e9968
Reviewed-on: https://chromium-review.googlesource.com/391938
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
