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UPSTREAM: AGESA f14: Fix MemContext buffer parser for AmdInitPost()
Memory training data that is saved as part of S3 feature in SPI
flash can be used to bypass training on normal boot path as well.
When RegisterSize is 3 in the register playback tables, no register is
saved or restored. Instead a function is called to do certain things in
the save and resume sequence. Previously, this was overlooked, and the
pointer containing the current OrMask was still incremented by 3 bytes.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ifeca0a8ab69209a4ce9c78cbdc97c82563a5f5ee
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c91ab1cfce
Original-Change-Id: I7221a03d5a4e442817911ba4862e3c0e8fa4a500
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19041
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/471462
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1 changed files with 7 additions and 3 deletions
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@ -347,7 +347,9 @@ MemMRestoreDqsTimings (
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if (!MemMSetCSRNb (&NBArray[Node], Reg->SpecialCases, PciAddress, *((UINT32 *) OrMask) & Reg->RegisterList[j].AndMask)) {
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return FALSE; // Restore fails
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}
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OrMask += (Reg->RegisterList[j].Type.RegisterSize == 0) ? 4 : Reg->RegisterList[j].Type.RegisterSize;
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if (Reg->RegisterList[j].Type.RegisterSize != 3)
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OrMask += (Reg->RegisterList[j].Type.RegisterSize == 0) ? 4 :
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Reg->RegisterList[j].Type.RegisterSize;
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}
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if (MaxNode < Node) {
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@ -370,7 +372,9 @@ MemMRestoreDqsTimings (
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if (!MemMSetCSRNb (&NBArray[Node], CReg->SpecialCases, PciAddress, *((UINT32 *) OrMask) & CReg->RegisterList[j].AndMask)) {
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return FALSE; // Restore fails
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}
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OrMask += (CReg->RegisterList[j].Type.RegisterSize == 0) ? 4 : CReg->RegisterList[j].Type.RegisterSize;
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if (CReg->RegisterList[j].Type.RegisterSize != 3)
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OrMask += (CReg->RegisterList[j].Type.RegisterSize == 0) ? 4 :
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CReg->RegisterList[j].Type.RegisterSize;
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}
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}
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} else if (((State == ST_PRE_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_MSR_PRE_ESR)) ||
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@ -606,4 +610,4 @@ MemMCreateS3NbBlock (
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}
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}
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}
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}
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}
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