Commit graph

26 commits

Author SHA1 Message Date
Ronald G. Minnich
ce5a0d5574 with VSA operating correctly. This is tested with AMD's recently
released new-model VSA code. 


Changes:
Index: util/dtc/flattree.c
Add an ID entry for apic properties.

Index: northbridge/amd/geodelx/apic
This is a new dts for the northbridge used as an APIC.

Index: northbridge/amd/geodelx/pci
This is a new dts for the northbridge used as a PCI device.

Index: northbridge/amd/geodelx/geodelx.c
Fix a non-obvious bug: we had set phase3 scan bus for both the 
domain AND the PCI device, which is a mistake: can't scan from the 
PCI device too. 

Index: northbridge/amd/geodelx/domain
This is a new dts for the northbridge used as an pci domain.
Created via svn move dts domain

Index: device/pci_device.c
If there are leftover devices, it is now a warning, not an error, 
since there are 
some no-pci devices in the tree now. For future: only complain about
leftover PCI devices ...

Index: device/device.c
make devcnt a global and initialize it in init_dev. Add a debug printk. 

Index: mainboard/pcengines/alix1c/dts
Add an 'apic' entry for the mainboard. This actually looks pretty clean
to me, the way it went in. 

Index: northbridge/amd/geodelx/vsmsetup.c
Delete all pcibios int support, no longer needed for VSA. 

Please note that this patch includes Carl-Daniel's improvements 
below, which I have Ack-ed. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

A few minor comments. It would be great if you could address them before
committing.

northbridge/amd/geodelx/domain is a copy of northbridge/amd/geodelx/dts.
You probably want to use "svn mv" for that because it preserves history
and the old file was probably intended to have been moved, not copied.

northbridge/amd/geodelx/vsmsetup.c:247: warning: ‘biosint’ defined but
not used
Since the new VSA does not use BIOSINT services anymore, deleting
biosint and related functions from vsmsetup.c would shrink vsmsetup.c by
one fourth. Patch follows (could you merge it into your patch?):

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@571 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-01 20:35:53 +00:00
Stefan Reinauer
6220b632e7 Now version 3: LinuxBIOS -> coreboot rename.
- I left LB_TAG_ intact because they are used by the payloads
- file renames are still missing. see next commit
- some lb_ renames might be missing. feel free to provide patches.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@564 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-01-27 18:54:57 +00:00
Ronald G. Minnich
7c1623aec3 include/device/device.h:
Change the ID constants so they are more useful for debugging. 
Instead of simple 1,2,3 they now are a 4-byte value which can be more
useful when looking at memory with a debugger. Lots of variables can be 
'1', but fewer variables will match to 'PCID'. 

include/device/pci.h: 
Include pci_ids.h in pci.h

device/device.c: remove silly comment. Change memcpy to struct assign, this makes it possible 
for the C compiler to do type checking. Add assign for the dev->id. 

flattree.c: Support the use of 'domainid' and 'pciid' in the per-chip dts. These IDs will be assigned
to the static tree device struct. In conjunction with the earlier patch, this change removes the need
for users to assign the ops struct member in the dts by hand, as it is done in the qemu port today. 
The ops struct member will automatically be assigned by the dev_init function, which is run 
in stage2 before any actual device code is run. (This change to dev_init was in the previous patch). 
Added two comments that document what is going on. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@557 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-01-19 06:29:14 +00:00
Stefan Reinauer
387412a0fa This patch fixes compilation on OS X
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@456 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-07-16 22:42:21 +00:00
Uwe Hermann
315c053116 Rename 'mainboard-part-number' to 'mainboard-name'.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@416 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-06-29 15:23:52 +00:00
Ronald G. Minnich
79351866e4 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com
Acked-by: Stefan Reinauer <stepan@coresystems.de

This patch adds artec dbe61 support, removes all mainboard.c, and
 adds
 the code to dtc so that it takes these properties from the top level
 dts:
 /{
 .
 .
 .

      mainboard-vendor = "AMD";
      mainboard-part-number = "Norwich";
 }

 statictree.h will have:
 extern const char *mainboard_vendor, *mainboard_part_number;

 and statictree.c will have:
 const char *mainboard_vendor = "AMD";
 const char *mainboard_part_number = "Norwich";

 It is an error to NOT have the vendor and part number in the top
 level dts.

 thanks

 ron

Get rid of mainboard.c in all mainboard directories.
Modify dtc so that it creates declarations (in statictree.h) and
generates the char *
for mainboard name and part # (in statictree.c).

Failure to set up a mainboard-vendor
OR mainboard-part-number property in the mainboard dts will get a
helpful and descriptive error message (tested).
This may be a first for the linuxbios config
tools.

Add Georgi's patch for the bug in flattree.c; assign *cp = 0.




git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@394 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-06-28 16:21:38 +00:00
Ronald G. Minnich
b38118c224 This is the dtc update by itself.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@368 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-06-27 19:13:18 +00:00
Ronald G. Minnich
14cc48b773 Changes to allow us to use the dtc to create C structures for the static
tree. Now requires newer flex, 2.5.4 at least.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Stefan Reinauer <stepan@coresystems.de>

M    dtc/dtc-lexer.l
M    dtc/flattree.c
M    dtc/dtc.h
M    dtc/livetree.c
M    dtc/fstree.c
M    dtc/dtc-parser.y


git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@361 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-06-19 07:03:35 +00:00
Stefan Reinauer
f1bc5438c6 cosmetic fixes for gcc pointer sign warnings (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@295 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-04-28 11:06:54 +00:00
Uwe Hermann
92a68191ba Here is a cleanup patch, removes 3 warnings from dtc build and some
commented-out code from stage0_i586.S. I am leaving the warnings about
gnu bintools in stage0_i586.S, just to make sure everyone knows why
some of the code is written the way it is, and nobody makes a mistake
in two years ...

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@244 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-03-11 19:54:30 +00:00
Stefan Reinauer
6869f4a129 new device model from Ron
This tree shows the new model. It demonstrates the constructor array
in use, for devices that are and are not specified in the dts. It
introduces a new generic structure, device_id, analogous to
device_path, which can describe all the types of device IDs we have.
It shows a way to set up arrays of structs, in the dts, for the
constructors, so we avoid ldscript hacks.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@233 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-03-10 15:55:41 +00:00
Stefan Reinauer
273a9b4356 Fix some compiler warnings.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@202 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-03-06 12:46:32 +00:00
Stefan Reinauer
ed26e22f02 fix warnings (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@193 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-03-05 22:01:28 +00:00
Ronald G. Minnich
53283b1e36 fix a stupid bug in malloc.
add debug printks. 

make dtc put 'root' as the first_node, instead of making the last node
be the first node .... much happier in linuxbios. 

sprintf is broken ... dammit. I hope someone will fix it. I've got about
another week of full-time I can spend on this and then I go back to part
time. So I'm going to need some help soon.

other fixups, and also, make the dts conform to the needs of the device
tree. So we have a domain0 and a device (0,0) that is the north. 

Mostly things are working, but we're STILL not getting any memory in the
LB tables from the north. The device tree is a bitch. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@175 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-03-03 00:39:30 +00:00
Ronald G. Minnich
637e4588be add pci ops so that we can do something.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@172 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-03-02 18:17:02 +00:00
Ronald G. Minnich
7f949f70f5 This set of changes gets us here.
Phase 1: done
Phase 2: early setup ...
Phase 2: done
Phase 3: Enumerating buses...
qemu-x86 enable_dev done
dev_phase3_scan: scanning Root Device
scan_static_bus for root(Root Device)
cpus: Unknown device path type: 0
cpus() enabled
i440bxemulation_enable_dev: 
i440bxemulation_enable_dev: DONE
northbridge_intel_i440bxemulation() enabled
northbridge_intel_i440bxemulation() scanning...
dev_phase3_scan: scanning 
pci_scan_bus start
PCI: pci_scan_bus for bus 00
PCI: scan devfn 0x0 to 0xff
PCI: devfn 0x0
PCI: pci_scan_bus pci_scan_get_dev returns dev <NULL>

Change dts compiler to emit a new struct member, dtsname, for devices,
so we can get actual useful names for things. 

Several mods and printks added. 

printk(BIOS_SPEW
gives no output for reasons I don't understand. 

Next in line is bringing back v2 support for pci, but not doing it the
way v2 does it. 

note the cpus() printk above. cpus don't have a valid path yet. 

We still need to work out the dts syntax for systems with multiple links
(opteron)

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@163 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-03-01 09:20:25 +00:00
Ronald G. Minnich
b520f3201e Some serious changes to get qemu working with pci.
Also added comments. 

A big change is in the dts. In OFW trees, the hierarchy seems to be:
/root/cpu/northbridge 
          south
          other pci

note that the north is in the hierarchy under the south. This hierarchy
makes no sense on systems with a shared frontside bus, or at least I
don't see how it can. In those systems, it's easier to think about 
the CPUs AND northbridges as children of the front side bus. 

in LinuxBIOS, it has always been this:
/root/cpu/whatever
/root/northbridge/
                  south
                  other pci

There have been many discussions over how it ought to be, for 8 years
now, and we've always come back to how LB does it. So I have changed the 
dts for qemu for now to match LB's way of doing things. Note that the
new system is flexible enough that, on K8, we CAN do things as above:
/cpu@0/amd8knorthbridge/etc.
/cpu@1/amd8knorthbridge/etc.

But on qemu, for now, the root is the mainboard, and the CPU and
northbridge are siblings. 

I've added some informational printks, cleaned up pci_ops, and done
other things so that it builds and all seems to work -- until it hangs
hard in enumeration in i440bx ...

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@160 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-02-28 19:17:59 +00:00
Uwe Hermann
b68d589126 s/linuxbios/LinuxBIOS/ in a number of places (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@124 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-02-26 01:19:39 +00:00
Stefan Reinauer
39a8f1f159 get rid of all warnings but one (lb table fake)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@107 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-02-23 15:35:42 +00:00
Ronald G. Minnich
01d7545b50 Set up default root device. Fix up printk stuff.
Fix up dts to set up ops struct member. Fix dts for qemu mainboard. 
We are getting past stage2 now, it is time for elfboot. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@88 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-02-23 10:38:22 +00:00
Stefan Reinauer
b4a7dad494 Clean up nasty dtc warnings
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@87 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-02-23 10:13:24 +00:00
Ronald G. Minnich
3b79d32caf This is an incredibly long commit message, but I want it in here as I
expect to hear about this change. Note that Stefan and I have discussed
this change and feel it is at least worth trying. 

Also, please be aware that this change is backed by a
lot of experience with LinuxBIOS users and usage of the last 7 years. 

First I detail changes, then I detail why. 


Major changes for the new config system. 
Selection of object files, and variable setting, is now controlled by
Kconfig. 

There is only one dts now. It is in the mainboard file. It may later 
move to the target file -- we will see. 

The dts is in two parts, seperated by %%. The first part is a 
fairly standard dts, and the dtc will automatically generate a device 
tree from it. The device tree is composed of generic structures. These 
structures are identical to those of the old V2 device tree. All the 
hierarchy and parent/child/sibling relationships appear to be correctly
generated. This means that all the v2 code will work without change. 

For each node in the tree, if the node has a  property named 'config', 
then the dtc will generate a reference to a structure and an include
directive for a path -- much as in the old Config tool. 

Example: here is a fragment of a dts
==========
north {
        config = "northbridge,intel,i440bx";
};

%%

struct northbridge_intel_i440bx_config north = {
        .whatever = 1;
};
===========

The dtc will create:
#include <northbridge/intel/i440gx/config.h>
struct northbridge_intel_i440bx_config north = {
        .whatever = 1;
};

struct device dev_north {
        .chip_ops = &northbridge_intel_i440bx_ops;
        .chip_info = &north;

        .
        .
        .
};

So the programmer specifies the tree structure in dts form, indicates
which devices have a config entry, and sets up the C code for the
config. I have worked with this and am finding it very easy to use. I
think this is the way to go. Plus, we are getting rid of most of the 
include hell of the old Config system. 

Note that the config node is OPTTONAL! If you do not set it then no
structure usage/include will occur. 

WHY? 
Here is my setup for v3. I think this is good. I like it and am
finding it easy to work with.

Basically, the old config system combined makefile generation, tree
generation, and chip struct initialization in one file -- config.lb.

What we need are four things:
1. selection of .c files to build the bios with
2. the device tree -- this is built with generic structures defined in
include/device/device.h
3. The per-chip structures, usually defined in, e.g.,
northbridge/intel/i440bx/chip.h
4. setting of variables such as baud rate, etc.

Again, this was all done in Config.lb, spread all over the place, like this:
config chip.h
object superio.o

This was hard for people. So we moved the makefile stuff out into the
Kconfig system. This change eliminates (1) and (4) above.

OK, what's left? Well, with our plans from last October, we had device
object model tree stuff, AND still had chip struct initialization in
one file. (2) and (3) above. This is tough, because I was fighting the
mapping of DTS stuff to the C code. It was getting just as ugly as the
old Config.lb. I have been struggling with this for months and it just
wasn't going anywhere.

But it's way too hard to set up the device tree by hand -- I've tried
it. OTOH, it's really easy to set up the per-chip stuff by hand --
I've tried that too. I did a search via:
find ~/src/LinuxBIOSv2/src/ -name chip.h -print
and looked at them all. These files are really simple. There's no
reason to get too tricky, as there is nothing worth getting tricky
about. The problem is the device tree, not these simple chip info
structs.

So, here's the solution.

The ONLY dts is in the mainboard directory. There is no equivalent of
Config.lb in the south, north, cpu, all that stuff any more. The
Kconfig and Makefile in those directories replaced the build-related
functions of Config.lb.-- (1) and (4) above.  The only thing left was
chip.h anyway (3) above.

But how can we express the settings in chip.h via the DTS? IT's been
very hard to get this going.

So, here is the trick. The dts in the mainboard directory divides into
two parts. The first part is the standard dts. The second part is the
C code. They are seperated, as in lex and yacc, with a %%.

Here is the dts for qemu (note that the cpus keyword is still not
right, and maybe this structure needs to change; i'm not that worried
about that too much, just the big picture I'm discussing here). Also,
note I'm working with some new properties, e.g. pcipath and pcidomain
-- if these properties exist ina node, then I create initialized
structure members for them. Also see enabled and on_mainboard --
properties, but I catch them and use them.
/{
       cpus {
               config="mainboard,emulation,qemu-i386";
               emulation,qemu-i386@0{
                       enabled;
                       on_mainboard;
                       device_type = "cpu";
                       name = "emulation,qemu-i386";
                       pcidomain = "0";

                       /* the I/O stuff */
                       northbridge,intel,440bx{
                               pcipath = "0,0";
                               southbridge,intel,piix4{
                               };
                       };
               };
       };


};

%%
/* the user sets up these structs */
struct mainboard_emulation_qemu_i386_config cpus = {
               .nothing = 1,
};

You can see the device tree stuff at top. If a given node has a
property named 'config', then that means what the old 'chip' thing
meant in Config.lb. The dtc will generate an #include to pull in a
file with the path name specified in the config property. The dtc will
not set up the per-chip struct, but it will set up a pointer to a
struct when it sets up the device tree. Note that at bottom, it's up
to you to set up the initialized struct. But this was always the easy
part anyway. Instead of wacky pseudo-C like we had in config.lb, we
just do real C. It's easy. Here is what the dtc generates.

#include <device/device.h>
#include <device/pci.h>
#include <mainboard/emulation/qemu-i386/config.h>
struct device dev_southbridge_intel_piix4;
struct device dev_northbridge_intel_440bx;
struct device dev_emulation_qemu_i386_0;
struct device dev_cpus;
struct device dev_root;
extern struct chip_operations mainboard_emulation_qemu_i386_ops;
struct mainboard_emulation_qemu_i386_config cpus = {
.nothing = 1,
};

struct device dev_root = {
       .path =  { .type = DEVICE_PATH_ROOT },
       .links = 1,
       .link = {
               [0] = {
                       .dev = &dev_root,
                       .link = 0,
                       .children = &dev_cpus
               },
       },
       .bus = &dev_root.link[0],
};
struct device dev_cpus = {
       .chip_ops = &mainboard_emulation_qemu_i386_ops,
       .chip_info = &cpus,
       .links = 1,
       .link = {
               [0] = {
                       .dev = &dev_cpus,
                       .link = 0,
                       .children = &dev_emulation_qemu_i386_0
               },
       },
       .bus = &dev_root.link[0],
       .next = &dev_root,
};
struct device dev_emulation_qemu_i386_0 = {
       .enabled = 1,
       .on_mainboard = 1,
       .path = {.type=DEVICE_PATH_PCI_DOMAIN,.u={.pci_domain={ .domain = 0 }}}
,
       .links = 1,
       .link = {
               [0] = {
                       .dev = &dev_emulation_qemu_i386_0,
                       .link = 0,
                       .children = &dev_northbridge_intel_440bx
               },
       },
       .bus = &dev_cpus.link[0],
       .next = &dev_cpus,
};
struct device dev_northbridge_intel_440bx = {
       .path = {.type=DEVICE_PATH_PCI,.u={.pci={ .devfn = PCI_DEVFN(0,0)}}},
       .links = 1,
       .link = {
               [0] = {
                       .dev = &dev_northbridge_intel_440bx,
                       .link = 0,
                       .children = &dev_southbridge_intel_piix4
               },
       },
       .bus = &dev_emulation_qemu_i386_0.link[0],
       .next = &dev_emulation_qemu_i386_0,
};
struct device dev_southbridge_intel_piix4 = {
       .bus = &dev_northbridge_intel_440bx.link[0],
       .next = &dev_northbridge_intel_440bx,
};



This compiles just fine.

I think this is the right way to go, comments to me.

But, note, IT COMPILES. And it's simple. And, it will work with our
current device tree code!



Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@59 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-01-26 17:30:40 +00:00
Ronald G. Minnich
c65898c00b Wrong syntax for initialisers, now fixed.
signed-off-by: ronald g. minnich


git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@31 f3766cd6-281f-0410-b1cd-43a5c92072e9
2006-10-19 23:26:10 +00:00
Ronald G. Minnich
0cfd87938b fix up initialisation. can an IBM person please take this back to IBM
and see if the -O lb produces structs that are in the least sensible? 
signed-off-by: Ronald G. minnich


git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@30 f3766cd6-281f-0410-b1cd-43a5c92072e9
2006-10-19 23:17:43 +00:00
Ronald G. Minnich
71651ca836 Fix the emit so that hex constants have a 0x preceding it
signed-off-by: Ronald G. Minnich


git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@28 f3766cd6-281f-0410-b1cd-43a5c92072e9
2006-10-19 15:39:00 +00:00
Ronald G. Minnich
a28296a6d2 filling in
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@2 f3766cd6-281f-0410-b1cd-43a5c92072e9
2006-10-06 19:19:14 +00:00