file-by-file changes:
dts:
There are no bus devices, remove it. Add the northbridge devices.
Fix susbsytem_vendor and subsystem_device.
southbridge/intel/i82371eb/ide:
Make the ide enabled by default.
northbridge/intel/i440bxemulation/i440bx.c:
1. Split ops into domain and northbridge
A. Domain should have bus ops, scan_bus, etc.
B. Northbridge should have ops for its own registers.
In this case it only needs read and set resources.
functions:
i440bx_read_resources - set up the IO and VGA resources. VGA is fixed.
i440bx_ram_resources - this should be called after resource assignment.
i440bx_set_resources - call pci_set_resources then i440bx_ram_resources.
i440bx_domain_read_resources - Set up system-wide resources, and
reserve space for the local APIC. I put the IOAPIC here too,
but it belongs somewhere in the southbridge.
i440bx_domain_set_resources - Mark the domain-specific resources as
stored (In a real device you'd probably need to set some
registers here.) Call phase4_set_resources for children.
southbridge/intel/i82371eb/i82371eb.c:
1. Add ISA read and set resources to reserve legacy IO space.
- Note that since it's subtractively decoded, it doesn't need
to be stored anywhere. It needs to be marked stored so
pci_set_resource doesn't try to store it.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1092 f3766cd6-281f-0410-b1cd-43a5c92072e9
a user/developer to disable the option table, so it doesn't overwrite whatever
the factory BIOS has written. Also fix building with OPTION_TABLE disabled.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1078 f3766cd6-281f-0410-b1cd-43a5c92072e9
pci_set_resources. There is no matching pci_bus_set_resources, so it's
confusing to see the dev function in the bus structures.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1048 f3766cd6-281f-0410-b1cd-43a5c92072e9
Most substantive change is getting rid of 'initialized', which was only
ever needed in v2 due to an implementation mistake.
With Uwe's comments taken into account,
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@961 f3766cd6-281f-0410-b1cd-43a5c92072e9
cleanups/fixes.
Fixup device tree code. Add/change methods as needed.
This should help serengeti.
Signed-off-by: Ronald G. Minnich<rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@954 f3766cd6-281f-0410-b1cd-43a5c92072e9
have a CAR area outside the usual RAM area. For those processors, we
have to implement a stack copying and switching mechanism. Since gcc
can't be told that the stack just moved, split stage1_main() into
stage1_phase1() and stage1_phase2() and stage1_phase3().
stage1_phase1() is the new entry point in stage1 and will handle
everything up to the point where we want to disable CAR.
Switching the stack, disabling CAR and handling other tasks related to
the stack switch (printk buffer move) is all wrapped in the
stage1_phase2() function.
stage1_phase2() calls disable_car() which then calls stage1_phase3().
stage1_phase3() is the former second half of stage1_main().
Notes about this patch:
- Code flow is almost unchanged for Qemu, K8 and Geode. No extensive new
testing required.
- We can support stack-keeping and stack-relocating architectures at the
same time, so C7 is definitely supportable
- The comment in stage1_phase2 says "some of this is not yet done". That
refers to the nonexisting code for stack switching on C7.
- "Minimal changes, maximum benefit".
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@932 f3766cd6-281f-0410-b1cd-43a5c92072e9
external Super I/O.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@846 f3766cd6-281f-0410-b1cd-43a5c92072e9
Fix the bus location for Qemu IDE.
This patch only provides the needed infrastructure for per-device
subsystem IDs, it does not hook them up to the PCI core yet, so this
patch is a no-op.
By the way, the on_mainboard property is activating lots of completely
untested code paths in v3, so someone might want to audit them.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@844 f3766cd6-281f-0410-b1cd-43a5c92072e9
The individual makefiles in lib/ mainboard/ southbridge/ and superio/
have been changed accordingly and the big glue layer in
arch/x86Makefile has been modified to wrap the new rules correctly.
This pepares the way for additional optimizations during compile and
link time.
Build tested and boot tested on Qemu.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@782 f3766cd6-281f-0410-b1cd-43a5c92072e9
it. Since it was the only content of the i440bxemulation northbridge
Kconfig, kill that file as well.
The i440BX RAM size is determined from the dts and the chipset specified
size is ignored. Print a warning for that, especially because v2 uses
the chipset specified RAM size.
Build and boot tested on qemu.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@766 f3766cd6-281f-0410-b1cd-43a5c92072e9
readability. Move to anonymous unions.
Build tested on all targets. Boot tested on qemu.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Ron tested this and it boots to Linux.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@730 f3766cd6-281f-0410-b1cd-43a5c92072e9
This creates a clearer distinction between source files in the source
tree we want to have compiled and indirectly created object/source files
in the object tree.
It also will make enable us to move to whole-program
optimization/compilation which should yield substantial size savings.
Then again, we may be able to do that without the makefile conversion as
well.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@714 f3766cd6-281f-0410-b1cd-43a5c92072e9
are not exactly in the best shape.
- MAINBOARD_NAME is claimed to be the mainboard name, but it is used
exclusively as mainboard directory.
- MAINBOARD_NAME is set in mainboard/$VENDOR/$BOARD/Kconfig to
$VENDOR/$BOARD, but mainboard/$VENDOR/Kconfig already hardcodes
$VENDOR/$BOARD as board path.
- MAINBOARD_NAME has a help text which will never be displayed to
the user.
The diffstat is encouraging: A total of 200 lines have been
removed completely.
Per-board Kconfig files have been deleted, the remnants making sense
have been merged into per-vendor Kconfig files and the never-shown help
texts have been removed.
If there are ever some real per-board options and not just tricks to
make the makefiles behave, we can resurrect the per-board Kconfig files.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@705 f3766cd6-281f-0410-b1cd-43a5c92072e9
is the logical continuation of r416 which happened a year ago.
As an added bonus, we now have consistent naming again, making grepping
the source for dts properties possible.
Build tested on all targets. Patch attached for Gmail users.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@697 f3766cd6-281f-0410-b1cd-43a5c92072e9
mainboard-name naming has been postponed because it's not clear what the
real name should be.
Generated code is identical to the state before the patch.
Compile tested.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@694 f3766cd6-281f-0410-b1cd-43a5c92072e9
Compile tested including boundary cases.
Runtime tested on dbe62 by Ron. Works fine.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@693 f3766cd6-281f-0410-b1cd-43a5c92072e9
code boots and works on qemu and
alix1c. It represents a huge change and a huge improvement. There are a
few fixes left to do, which
will come once this is in.
This change started out easy: get the device IDs OUT of the the dts, and
into one place. We
decided the device IDs should be in the constructors ONLY. To make a
long story short, that just did
not work out, and it revealed a flaw in the design. The result?
- no more ids in the various dts files.
- the constructor struct is gone -- one less struct, nobody liked the
name anyway
- the device_operations struct now includes the device id.
- constructor property no longer used; use device_operations instead.
- lpc replaced with ioport
All the changes below stem from this "simple" change.
I am finding this new structure much easier to work with. I hope we're
done
on this for real, however!
TODO:
1. Change limitation in dtc that makes it hard to use hex in pci@
notation.
Now for the bad news. Sometime today, interrupts or io or something
stopped working between r596 and r602 -- but I did no commits at
that point. So something has gone wrong, but I don't think it's this
stuff.
I did try a build of HEAD, and it fails really, really badly. Much
more badly than this fails, so I think this commit is only going
to improve things. It does work fine on qemu, fails on alix1c,
so I suspect one of today's "clean up commits" broke something.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@603 f3766cd6-281f-0410-b1cd-43a5c92072e9
in dts. This gets rid of the ugly pcipath etc. properties.
So, instead of
somedevice {pcipath="1,0";};
We say pci@1,0{ etc. etc. };
As per my agreement I agree to document this in the design doc.
The alix1c compiles but is untested, and will probably need some work.
I will do these additional tasks on friday.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
M include/device/path.h
Add LPC path type, replacing SUPERIO path type, since SUPERIO is only
one type of LPC. Clean up tabbing in parts of the file (cosmetic).
M mainboard/emulation/qemu-x86/dts
Modify this dts for the new path naming scheme.
M device/pci_device.c
Change what used to be a BIOS_ERR (but is no longer) to a BIOS_NOTICE.
The change is that the device tree includes more than just PCI devices,
so finding a non-PCI device is no longer fatal; a notice is useful.
M device/device_util.c
Add string creation for PCI_BUS nad LPC.
M northbridge/intel/i440bxemulation/dts
Add ID info for the chip.
M northbridge/intel/i440bxemulation/i440bx.c
Change initialization so it is explicitly for the .ops struct member.
M util/dtc/flattree.c
Add support for the new path naming scheme.
I'm in the middle of this commit so I'll fix the hard-coded lengths
next commit.
Also delete dead code between #if 0 and /* and //
M util/x86emu/vm86.c
comment out unused variables. these may someday be use, not ready
to delete them yet.
M Makefile
Change -O2 to -g. We need debugging on LAR far more than we need performance.
git-svn-id: svn://coreboot.org/repository/coreboot-v3@593 f3766cd6-281f-0410-b1cd-43a5c92072e9
to a board should add a defconfig in mainboard/vendor/board/defconfig.
I think that the defconfig should:
1. Use the ROM size that comes with the board
2. Enable compression
3. Not include a payload
This will make it easy for buildrom or anyone who wants to build it
manually to use lar to add their payloads. It also allows buildrom to
keep the configs in the coreboot tree.
The patch also adds mainboard/emulation/qemu-x86/defconfig
Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@578 f3766cd6-281f-0410-b1cd-43a5c92072e9
Due to some problems with PCI transactions, Geode LX needs the ROM cache properties to be write-serialize + cache disabled by runtime. More details below.
Add mainboard_pre_payload() call to each mainboard as the final coreboot function before the payload is called by stage1.
Note that this patch also grows the bootblock from 16K to 20K to make room for mainboard_pre_payload().
"The problem is a transaction depth issue and bottlenecks inside the GX
and LX that go across PCI. The conditions are very complicated but it
comes down to we need write serialization for writes to PCI. If you
look in the data book you can't have write serialization and the cache
enabled on a given area. During coreboot we don't have to worry about
a write or a PCI bus master so I think we can enable caching the ROM.
After coreboot we can't be sure what will happen in the system so we
need to set it up to be safe. For example flashrom just clears the
write protect bit. If the cache were enabled (no write serialization)
and flashrom was writing the ROM we would be in a precarious position.
A PCI bus master doing a read or a write that has a hit on a tag
would cause enough bottleneck conditions that it might hit the bug. We
could change flashrom but that doesn't help other tools. We need to
leave the system in a safe state. Also, caching the ROM after it is no
longer used doesn't make much sense. So, we need a call just before
the payload runs to clean up the system."
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@573 f3766cd6-281f-0410-b1cd-43a5c92072e9
- I left LB_TAG_ intact because they are used by the payloads
- file renames are still missing. see next commit
- some lb_ renames might be missing. feel free to provide patches.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@564 f3766cd6-281f-0410-b1cd-43a5c92072e9
_MAINOBJECT #defined. Calls from all other files ended up in nirvana
because the compiler was not able to calculate the address of the
wrapper for the absolute call. The linker tried, but failed miserably.
Use the -combine flag and compile all of initram at once. This enables
GCC to calculate the address of the abscall wrapper, resulting in
working code.
Segher Boessenkool thinks the patched code works only by accident
because GCC has no way to specify generation of XIP code. According to
him, future GCC versions or other circumstances may break the code.
While this patch makes code work for now, it does NOT check whether the
generated code tries to write to memory outside the stack (general
writable data). That will of course fail, but I hope porters are smart
enough to avoid that.
Corey Osgood writes:
Great work tracking this down! This is okay for now, but we need to look
for a better solution in the future. Counting on porters who may or may
not remember this discussion to avoid something isn't good
future-proofing.
Checking the ELF sections for read-write data and stopping the build
with an error could make this future-proof.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@537 f3766cd6-281f-0410-b1cd-43a5c92072e9
may be due to miscompilation of XIP objects which do not have
_MAINBOBJECT defined. This issue was impossible to see on qemu because
no such object existed. Introduce initram_printktest.c in the Qemu
target, which will test for miscompilation and crash with a descriptive
error message.
This has been build tested and runtime tested on Qemu, and with my
compiler/linker combination it indeed crashes.
gcc (GCC) 4.2.1 (SUSE Linux)
GNU ld (GNU Binutils) 2.17.50.20070726-14 (SUSE Linux)
Trying with gcc-4.1 (GCC) 4.1.3 20070724 (prerelease) (SUSE Linux) and
the linker above had exactly the same results.
Unless we manage to fix the bug uncovered by this patch, leaving the
Qemu target in crashing state is the best thing we can do because this
behaviour mirrors the state of all other targets.
Ron says: I am comfortable with this. If hardware is broken, qemu should
be broken. I avidly wait the fix :-)
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@535 f3766cd6-281f-0410-b1cd-43a5c92072e9
across all of these makefiles. The rules are now in order of execution
during boot, that is:
STAGE0_MAINBOARD_OBJ
INITRAM_OBJ
STAGE2_MAINBOARD_OBJ
As added benefit, mainboard makefiles are now almost identical.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@533 f3766cd6-281f-0410-b1cd-43a5c92072e9
the x86 arch makefile. This makes porting to a new mainboard less
confusing.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@529 f3766cd6-281f-0410-b1cd-43a5c92072e9
and create a valid LAR header with an entry value. This will fix the
problems Ron is having on the ALIX 1C and probably allow it to boot.
It also sets the text base of the .o to 0, instead of whatever wacky
value gld is choosing, so all platforms will have the same value.
Get away from worrying about potential gld bugs, now and in the future.
As added benefit, we obsolete a lot of code without introducing
new code.
Qemu target entry point debugging has been added to be able to spot
problems with entry points in the future.
This patch is a joint work of Ron and Carl-Daniel.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@523 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@519 f3766cd6-281f-0410-b1cd-43a5c92072e9
Makefiles clean and simple.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@517 f3766cd6-281f-0410-b1cd-43a5c92072e9
had _SHARED defined during compilation, each of them would contain an
assignment of stage0_printk to *printk. During linking, this caused
errors as multiple definitions of printk existed.
Make sure _SHARED alone gives you only the printk prototype, and iff
_MAINOBJECT is defined as well, include the assignment.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@516 f3766cd6-281f-0410-b1cd-43a5c92072e9
This fixes for example printk calls from initram code.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@505 f3766cd6-281f-0410-b1cd-43a5c92072e9
* statically link linuxbios.initram for now (depends on printk, post_code
and die)
* greatly simplify all makefiles by creating a global Rules.make
* use $(dir $@) in Makefiles instead of absolute paths for mkdir..
* clean up Makefiles by calling components' code locally instead of in the
Makefile. (Remember: one day, no code per mainboard)
* unconditionally create .xcompile in case it changed
* add NM to xcompile
* create $(obj)/linuxbios.map with all symbols of all stages
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@463 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@459 f3766cd6-281f-0410-b1cd-43a5c92072e9
- PCI_VENDOR_ID_CIRRUS
- PCI_DEVICE_ID_CIRRUS_5446
Some minor cosmetic fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@447 f3766cd6-281f-0410-b1cd-43a5c92072e9
Will be re-added as soon as we support PowerPC in v3, of course.
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@442 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@416 f3766cd6-281f-0410-b1cd-43a5c92072e9
all the early_*
stuff to stage1. All targets build and qemu boots.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@414 f3766cd6-281f-0410-b1cd-43a5c92072e9
Get dbe61 initram into buildable shape. This depends
the msr_t patch which is in the pipeline.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@395 f3766cd6-281f-0410-b1cd-43a5c92072e9
Acked-by: Stefan Reinauer <stepan@coresystems.de
This patch adds artec dbe61 support, removes all mainboard.c, and
adds
the code to dtc so that it takes these properties from the top level
dts:
/{
.
.
.
mainboard-vendor = "AMD";
mainboard-part-number = "Norwich";
}
statictree.h will have:
extern const char *mainboard_vendor, *mainboard_part_number;
and statictree.c will have:
const char *mainboard_vendor = "AMD";
const char *mainboard_part_number = "Norwich";
It is an error to NOT have the vendor and part number in the top
level dts.
thanks
ron
Get rid of mainboard.c in all mainboard directories.
Modify dtc so that it creates declarations (in statictree.h) and
generates the char *
for mainboard name and part # (in statictree.c).
Failure to set up a mainboard-vendor
OR mainboard-part-number property in the mainboard dts will get a
helpful and descriptive error message (tested).
This may be a first for the linuxbios config
tools.
Add Georgi's patch for the bug in flattree.c; assign *cp = 0.
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@394 f3766cd6-281f-0410-b1cd-43a5c92072e9
