The reset value for NAND timings is the slowest possible for Flash interface.
Implement optionally setting it to a different value inside the NAND device.
Set it to appropriate values for Artec Group DBE61 and DBE62.
This results in a roughly two times quicker read time as measured by hdparm
for these boards.
Because we can not cast to southbridge_amd_cs5536_nand_config if the board dts
does not have an entry for the NAND device, this change proposes a method for
reasonably clean way to only optionally compile in support for certain devices:
If a board wants to support an optional device, its Kconfig entry can select
that configuration. If it's optional even across the same board, it can expose
a subconfig option of the board, that describes it and if chosen selects the
device config. The source code for that device is conditionally compiled only
if the Kconfig option gets enabled by the configuration for the board.
A requirement is that if the board configuration can enable a device, it is
contained in the boards dts file as well.
A perhaps better long-term alternative for this could be making dtc generate
preprocessor definitions for each device_configuration struct that it creates.
Then the source code file is always enabled, but that file can be wrapped
around a simple #ifdef check in its entirety.
Conversion to the alternative approach from the short-term Kconfig approach
proposed here should be relatively easy, as to not block inclusion of the
Kconfig approach in the short term.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1138 f3766cd6-281f-0410-b1cd-43a5c92072e9
* Copying of files from other mainboards as a starting point:
amd/db800/Makefile
artecgroup/dbe62/cmos.layout
artecgroup/dbe62/dts
amd/db800/initram.c
artecgroup/dbe61/irq_tables.h
artecgroup/dbe62/stage1
* Kconfig integration. Behind CONFIG_EXPERIMENTAL for now, as the board is not in the market yet.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1119 f3766cd6-281f-0410-b1cd-43a5c92072e9
a user/developer to disable the option table, so it doesn't overwrite whatever
the factory BIOS has written. Also fix building with OPTION_TABLE disabled.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1078 f3766cd6-281f-0410-b1cd-43a5c92072e9
are not exactly in the best shape.
- MAINBOARD_NAME is claimed to be the mainboard name, but it is used
exclusively as mainboard directory.
- MAINBOARD_NAME is set in mainboard/$VENDOR/$BOARD/Kconfig to
$VENDOR/$BOARD, but mainboard/$VENDOR/Kconfig already hardcodes
$VENDOR/$BOARD as board path.
- MAINBOARD_NAME has a help text which will never be displayed to
the user.
The diffstat is encouraging: A total of 200 lines have been
removed completely.
Per-board Kconfig files have been deleted, the remnants making sense
have been merged into per-vendor Kconfig files and the never-shown help
texts have been removed.
If there are ever some real per-board options and not just tricks to
make the makefiles behave, we can resurrect the per-board Kconfig files.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@705 f3766cd6-281f-0410-b1cd-43a5c92072e9
* Linutop 2 is not a DBE62
* ThinCan is the trademarked brand name for the thin client line, not an alternate "also known as" name
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@668 f3766cd6-281f-0410-b1cd-43a5c92072e9
- I left LB_TAG_ intact because they are used by the payloads
- file renames are still missing. see next commit
- some lb_ renames might be missing. feel free to provide patches.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@564 f3766cd6-281f-0410-b1cd-43a5c92072e9
Acked-by: Stefan Reinauer <stepan@coresystems.de
This patch adds artec dbe61 support, removes all mainboard.c, and
adds
the code to dtc so that it takes these properties from the top level
dts:
/{
.
.
.
mainboard-vendor = "AMD";
mainboard-part-number = "Norwich";
}
statictree.h will have:
extern const char *mainboard_vendor, *mainboard_part_number;
and statictree.c will have:
const char *mainboard_vendor = "AMD";
const char *mainboard_part_number = "Norwich";
It is an error to NOT have the vendor and part number in the top
level dts.
thanks
ron
Get rid of mainboard.c in all mainboard directories.
Modify dtc so that it creates declarations (in statictree.h) and
generates the char *
for mainboard name and part # (in statictree.c).
Failure to set up a mainboard-vendor
OR mainboard-part-number property in the mainboard dts will get a
helpful and descriptive error message (tested).
This may be a first for the linuxbios config
tools.
Add Georgi's patch for the bug in flattree.c; assign *cp = 0.
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@394 f3766cd6-281f-0410-b1cd-43a5c92072e9
