Commit graph

43 commits

Author SHA1 Message Date
Marc Jones
f2872767a2 Add AP detection to stage0 to prevent APs from re-initializing mainboard setup
that has already been done by the BSP. For single processor systems the CPU
flag is always 0, BSP. This code also moves the AP stop for K8 mainboards to
after memory setup so the AP's MTRRs can be setup to match system memory.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1129 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-02-10 22:41:35 +00:00
Carl-Daniel Hailfinger
33de3b2fb5 Right now we face the problem that we can't support processors which
have a CAR area outside the usual RAM area. For those processors, we
have to implement a stack copying and switching mechanism. Since gcc
can't be told that the stack just moved, split stage1_main() into
stage1_phase1() and stage1_phase2() and stage1_phase3().
stage1_phase1() is the new entry point in stage1 and will handle
everything up to the point where we want to disable CAR.
Switching the stack, disabling CAR and handling other tasks related to
the stack switch (printk buffer move) is all wrapped in the
stage1_phase2() function.
stage1_phase2() calls disable_car() which then calls stage1_phase3().
stage1_phase3() is the former second half of stage1_main().

Notes about this patch:
- Code flow is almost unchanged for Qemu, K8 and Geode. No extensive new
testing required.
- We can support stack-keeping and stack-relocating architectures at the
same time, so C7 is definitely supportable
- The comment in stage1_phase2 says "some of this is not yet done". That
refers to the nonexisting code for stack switching on C7.
- "Minimal changes, maximum benefit".

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@932 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-16 03:00:28 +00:00
Carl-Daniel Hailfinger
f04465f343 Fix v3 GeodeLX stack and global variable pointer corruption.
We had a jump instead of a call to stage1_main in geodelx/stage0.S. That
means all accesses to bist and init_detected were off by 8 bytes and
collided with accesses to the global variable pointer.

Found during my cleanup runs.

This bug had the following effects:
1.) If gcc had decided to reload bist from stack after initializing the
global variable pointer, bist would have been nonzero, an indicator for
processor failure.
2.) If gcc had decided to use the stack location of bist as a scratch
register (and it probably is free to do so as long as the contents are
restored before returning), it would have clobbered the global variable
pointer, leading to NULL pointer dereferences.
3.) Any accesses to init_detected would have resulted in accessing 4
bytes above the top of stack (0x87ffc-0x87fff), something the rest of
the code deliberately avoids.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@909 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-08 16:12:32 +00:00
Carl-Daniel Hailfinger
73d4383d10 We have lots of bit-for-bit identical code in the various stage0
implementations. Factor out the 16 bit code with associated protected
mode activation.

I'm open to moving even more common code out, but this is a well-defined
start.

This cleanup has been prepared for by r902, r905 and r907.

Boot tested on qemu. Build tested on i586, geodelx, k8.

The diffstat is most enlightening:
 amd/stage0.S     |  145 ---------------------------------------------
 geodelx/stage0.S |  145 ---------------------------------------------
 i586/stage0.S    |  145 ---------------------------------------------
 stage0_common.S  |  145 +++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 148 insertions(+), 432 deletions(-)

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@908 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-08 16:07:29 +00:00
Carl-Daniel Hailfinger
96fcf12785 stage0 code for K8 and i586 has lots of mostly identical parts even in
CAR code.

Reduce the diff of the mostly identical parts to zero. That involves
changing comments, whitespace and instruction order.

Now we can split out the common parts more easily and concentrate on the
differences.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@907 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-07 23:53:02 +00:00
Carl-Daniel Hailfinger
ef06e83ef4 stage0 code for GeodeLX, K8 and i586 is mostly identical everywhere
except for the actual CAR code and inital #includes and #defines.

Reduce the diff of the mostly identical parts to zero. That involves
changing comments, whitespace and instruction order to the best variant
present in the 3 files.

Now we can split out the common parts more easily and concentrate on the
differences.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@905 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-07 21:59:21 +00:00
Carl-Daniel Hailfinger
7b5c1647f7 Make sure the reset vector code for K8, GeodeLX and i586 is
byte-for-byte identical. That makes factoring out easier.

Fix a duplicated BIST save for K8.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@902 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-06 23:26:29 +00:00
Ronald G. Minnich
be03d189db Finally, after two years, put in real code for stop_ap(). Code has to be
moved to stage1 ROM code. Make the struct for nodeid/coreid generic to 
x86. Create the functions for existing architectures are a model for 
future architectures (VIA coming soon we hope). 

Move includes so that things build correctly now. 

This is actually a small patch that impacted a number of files due to 
include order changes. This is build and boot tested on simnow and 
build tested on geode. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@872 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-29 14:58:56 +00:00
Carl-Daniel Hailfinger
08f7cd8688 stage1_main() calling conventions changed to use two parameters instead
of one. This resulted in a stack underflow for i586 and GeodeLX because
the stack was set up for only one parameter in their stage0 asm code.

Untested. Note that this didn't trigger on K8 because the stack setup
there has excessive room, something that should be fixed as well.

This is a band-aid and we should do it right instead. Discussion
follows:

Carl-Daniel Hailfinger wrote:
> Can't we determine init_detected from C code and avoid working with it
> in asm?
> The Fam10h BKDG states in section 2.3.1:
> "determine the type of this reset. One method is to use [The Link
> Initialization Control Register] F0x6C[InitDet] bit."
> The same register is suggested by the Athlon64/Operon BKDG and the
> Fam0fh BKDG.
> 
> That should work from C and make our lives easier. To be honest, I
> have no idea why we use bit 11 of MTRRdefType_MSR for the
> init_detected purpose.

Ron Minnich wrote:
> I plan to change that in future. For now, I want to change as little
> as I can, since this code is so mysterious anyway. I would say let's
> leave it in with a warning of some sort.


Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@838 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-28 02:55:14 +00:00
Carl-Daniel Hailfinger
e1138c9164 Typo: word duplication.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@803 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-22 11:33:19 +00:00
Carl-Daniel Hailfinger
1b5c399508 Move stage1 global variable management from asm to C. The stage0 asm
code now unconditionally pushes an empty pointer to the stack which is a
placeholder for the pointer to global variable storage. That pointer and
the global variable storage are initialized in global_vars_init().

Creating global variables is now a piece of cake. You don't even have to
touch any asm code, just add them to struct global_vars.

Build tested on all targets, boot tested on Qemu.

NOTES:
- The code is not yet MP safe, but that's due to v3 not being MP safe in
general (and the comments contradict the code regarding MP features).
- K8 code now works by accident.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Segher Boessenkool <segher@kernel.crashing.org>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@785 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-18 16:54:12 +00:00
Carl-Daniel Hailfinger
77010a1111 The named unions in the device tree code are obnoxious and degrade
readability. Move to anonymous unions.

Build tested on all targets. Boot tested on qemu.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Ron tested this and it boots to Linux.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@730 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-10 00:20:24 +00:00
Ronald G. Minnich
24d5ad5466 Trivial fix: fix include name for macros.h
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@719 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-04 00:39:28 +00:00
Ronald G. Minnich
935c99a3a9 minor include stuff.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>

Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@701 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-01 16:59:09 +00:00
Ronald G. Minnich
96914e1655 1. geodelx.c: cover case of unterminated DRAM by adding a terminated
parameter to two functions. 
2. geodelx.h: define DRAM_TERMINATED and DRAM_UNTERMINATED constants
3. dbe62/initram.c: move to auto PLL control, so set MANUALCONF to 0
4. all other initram.c: set up calls to cpu_reg_init with proper 
   TERMINATED/UNTERMINATED constants. 

builds for dbe62. The auto PLL strapping is tested and works. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@699 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-29 15:54:46 +00:00
Carl-Daniel Hailfinger
5a19770667 northbridge/amd/geodelx/raminit.c:auto_size_dimm() checks for the
mathematically impossible condition of a value being above and below the
specified range at the same time. Change it to check for out-of-range.
arch/x86/geodelx/geodelx.c:set_delay_control() is missing a break, it
will keep going and mess up DRAM timings.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Both changes look right to me.
Acked-by: Marc Jones <marc.jones@amd.com>


The raminit in v2 was fixed in r2899 | rminnich | 2007-10-26 with this
log:
> The lxraminit change fixes a bug (&& used instead of ||) [...]
> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
> Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@659 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-04-16 16:40:45 +00:00
Ronald G. Minnich
f7ad196c0a This started out as a trivial change and turned into a big change. This
code boots and works on qemu and
alix1c. It represents a huge change and a huge improvement. There are a
few fixes left to do, which 
will come once this is in. 

This change started out easy: get the device IDs OUT of the the dts, and
into one place. We
decided the device IDs should be in the constructors ONLY. To make a
long story short, that just did 
not work out, and it revealed a flaw in the design. The result? 

- no more ids in the various dts files. 
- the constructor struct is gone -- one less struct, nobody liked the
  name anyway
- the device_operations struct now includes the device id.
- constructor property no longer used; use device_operations instead. 
- lpc replaced with ioport

All the changes below stem from this "simple" change. 

I am finding this new structure much easier to work with. I hope we're
done
on this for real, however!

TODO: 
1. Change limitation in dtc that makes it hard to use hex in pci@
notation. 

Now for the bad news. Sometime today, interrupts or io or something
stopped working between r596 and r602 -- but I did no commits at
that point. So something has gone wrong, but I don't think it's this
stuff.

I did try a build of HEAD, and it fails really, really badly. Much
more badly than this fails, so I think this commit is only going
to improve things. It does work fine on qemu, fails on alix1c, 
so I suspect one of today's "clean up commits" broke something. 


Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@603 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-16 04:13:44 +00:00
Carl-Daniel Hailfinger
5d11489d74 Make printk() log to a buffer.
Tested on Qemu and Geode LX.
Benefits of this patch:
- printk() now works directly after printk_buffer_init(), even before
the serial port is set up.
- If all you want is a log, you don't have to bother with serial output.
- A payload can read and analyze the log.
- You can build on this and buffer log until serial is available, then
flush the messages buffered so far.

The printk buffer is configurable with a default-on Kconfig variable.

If you want to dump the buffer from the Qemu monitor after CAR has been
disabled, use this command:
memsave 0x90000 65536 memdump.bin

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Marc Jones <marc.jones@amd.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@590 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-13 15:48:37 +00:00
Ronald G. Minnich
575ca7374c This change moves the geodelxinit code from stage2 to stage1, which in
turn gets cache turned on much sooner. The system boots a bit faster. 

We're still far too slow, perhaps because we are not caching ROM? 

Index: arch/x86/Makefile
Add ../../northbridge/amd/geodelx/geodelxinit.o object
Index: arch/x86/geodelx/geodelxinit.c
add sizeram function. 
Index: arch/x86/geodelx/stage1.c
add called to northbridge_init_early()
Index: northbridge/amd/geodelx/Makefile
remove geodelxinit.o object
Index: northbridge/amd/geodelx/geodelx.c
remove call to northbridge_init_early()
remove sizeram function. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@572 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-04 16:16:16 +00:00
Stefan Reinauer
6220b632e7 Now version 3: LinuxBIOS -> coreboot rename.
- I left LB_TAG_ intact because they are used by the payloads
- file renames are still missing. see next commit
- some lb_ renames might be missing. feel free to provide patches.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@564 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-01-27 18:54:57 +00:00
Carl-Daniel Hailfinger
cc0b9f7917 After configuring the PLL registers on Geode LX, we have to reset the
processor. However, nothing in the log tells the user why the processor
is being reset.
Example log follows:

LinuxBIOS-3.0.0 Fri Jan 11 15:53:52 MST 2008 starting...
Choosing fallback boot.
[...]
Fallback failed. Try normal boot
LAR: Attempting to open 'normal/initram/segment0'.
[...]
LAR: CHECK normal/initram/segment0 @ 0xfffc49b0
start 0xfffc4a00 len 5564 reallen 5564 compression 0 entry 0x000010ca
loadaddress 0x00000000
Entry point is 0xfffc5aca
pll_reset: read msr 0x4c000014
_MSR GLCP_SYS_RSTPLL (4c000014) value is: 00000398:0000181e
Configuring PLL


LinuxBIOS-3.0.0 Fri Jan 11 15:53:52 MST 2008 starting...
Choosing fallback boot.
[...]


Print an informative message before resetting the processor.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@553 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-01-12 01:09:47 +00:00
Carl-Daniel Hailfinger
888063b4af These changes implement a fixed Geode LX Cache As Ram that allows a
return from disable_car.
- Move the cache as ram memory to 0x80000 instead of 0xc8000, as the C
  range is really tricky to get right :-)
- Modify the geode disable_car to ensure the cache is flushed to ram on
  the wbinvd.

With these changes, I get a payload loaded.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@546 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-01-04 23:19:49 +00:00
Carl-Daniel Hailfinger
cbbddbe4db Move AMD Geode LX defines for CAR from a .S to a .h so they are
available to C.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@543 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-01-04 12:53:09 +00:00
Ronald G. Minnich
9df08251e0 add one debug print, move all smbus_read_byte to spd_read_byte.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>


git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@527 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-11-27 16:47:34 +00:00
Uwe Hermann
497cdb7484 Constify structs which can be const.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@519 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-11-26 13:28:52 +00:00
Stefan Reinauer
c4d5d3861a small trivial patch to fix return types, printk warnings
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@467 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-08-18 23:31:09 +00:00
Uwe Hermann
7467eba22a Various code cleanups:
- Simplify lots of code, especially msr-related code.

 - Move struct msrinit declaration into msr.h as we use it quite often
   and there's no use to duplicate it again and again in each file.

 - Remove unrequired variable usage (e.g. numEnabled, msrnum, val, port).

 - Remove useless comments.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@464 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-07-23 23:18:41 +00:00
Uwe Hermann
7705f6a682 Various smaller code fixes:
- Use 'static' for functions and structs which are not meant to be public.

 - Use 'const' for variables which are not meant to be modified.

 - Move some prototypes into legacy.h where they belong.

 - Drop prototypes for non-existing functions.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@460 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-07-20 14:03:39 +00:00
Marc Jones
064cd70619 Stage0 and Stage1 improvements. Gets Geode LX into initram. Use LAR XIP. Add disable_CAR().
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com> 



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@459 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-07-19 15:15:57 +00:00
Uwe Hermann
96a2aac67e Minor fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@454 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-07-15 21:31:05 +00:00
Uwe Hermann
50cdf3827d Merge hlt() into cpu.h where it belongs. Add some documentation.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@449 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-07-12 13:01:42 +00:00
Uwe Hermann
6d2a927124 Remove some include files which are not required (and add some which are).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@448 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-07-12 01:26:43 +00:00
Uwe Hermann
8acc5d79ed Simplify the geodelx_msr_init() function by looping over a table.
Also, drop all copyright lines except (C) 2007 AMD, as this code is
a straight copy of msr_init() in the v2 Norwich target, and that file
only contains the (C) 2007 AMD line.

Finally, I think this patch also fixes a (copy+paste) bug, the MSRs
written should not be
   MSR_GLIU0_BASE1, MSR_GLIU0_BASE2, MSR_GLIU1_BASE1, MSR_GLIU0_BASE2
but rather
   MSR_GLIU0_BASE1, MSR_GLIU0_BASE2, MSR_GLIU1_BASE1, MSR_GLIU1_BASE2
(note MSR_GLIU0_BASE2 vs. MSR_GLIU1_BASE2)

Untested on real hardware, of course.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@445 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-07-11 19:42:21 +00:00
Uwe Hermann
203bffe9e7 Various coding style fixes, typo fixes, and other cosmetic changes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@438 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-07-07 21:18:47 +00:00
Marc Jones
22895ba000 Rework the Geode delay control setup to table driven and much more readable.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@435 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-07-06 18:03:43 +00:00
Marc Jones
7c9c8db800 Moved some generic 8254 PIT #defines out of the speaker code to legacy.h.
Use legacy.h PIT defines in Geode code.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@433 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-07-05 16:58:10 +00:00
Marc Jones
b1ef1489a0 Clean up comments and #defines in Geode LX code.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@432 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-07-03 20:33:33 +00:00
Ronald G. Minnich
e62540d291 1. move early_* names to stage1.c
2. rename *_early_init symbols to *_stage1
3. Rename early_init to hardware_stage1

now people can see when things are supposed to happen. 
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@407 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-06-29 00:09:24 +00:00
Ronald G. Minnich
c61a113dfb These are changes we are making so that serial startup can be done in
stage 1. This is part of a general change in startup due to the move
from V2 to V3. 

The LX is complex and in this case much work must be done, we don't
expect all platforms to be this way. 

We will probably be changined these names from eary_* to stage1.c
to make it easier for people to know what's going on.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@406 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-06-28 23:59:40 +00:00
Ronald G. Minnich
ce90131d23 struct msr replacement
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@398 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-06-28 17:05:46 +00:00
Uwe Hermann
2a605775a6 Various cosmetic license header fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@392 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-06-28 14:06:39 +00:00
Stefan Reinauer
98a84ef995 make cpu code future proof
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@387 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-06-27 21:07:10 +00:00
Stefan Reinauer
b89d99ddfd Ron's arch code., slightly changed. Another one will follow
These are changes needed for geode lx. Also, we are moving CPU bug fixes
into initram. This simplifies the code and, also, guarantees that
cpu bugs won't cause trouble to initram.

All LX targets compile. Most of these changes have been run by
the list.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@386 f3766cd6-281f-0410-b1cd-43a5c92072e9
2007-06-27 21:01:01 +00:00