From f79dac26318828f2d8093caf3d3dfba5e3321792 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Mon, 9 Jan 2017 12:13:52 -0600 Subject: [PATCH] UPSTREAM: amd/mct/ddr3: Fix incorrect DQ mask calculation On AMD DDR3 platforms, the upper DQMask was incorrectly calculated, leading to undefined behaviour and possible DRAM training faults. Use the correct calculation for the upper DQMask. BUG=none BRANCH=none TEST=none Change-Id: Ibefa976ee627cf5d2515bf3aa52f65795dc6e303 Signed-off-by: Patrick Georgi Original-Commit-Id: 21b01b80d6a11a24d69a3e7ccd7c113681b6dcee Original-Found-by: Coverity Scan #1347394 #1347393 Original-Change-Id: If3190eb7c30f1f00d6fd8b751bc1761c9d119782 Original-Signed-off-by: Timothy Pearson Original-Reviewed-on: https://review.coreboot.org/18068 Original-Tested-by: build bot (Jenkins) Original-Tested-by: Raptor Engineering Automated Test Stand Original-Reviewed-by: Martin Roth Original-Reviewed-by: Nico Huber Original-Reviewed-by: Paul Menzel Reviewed-on: https://chromium-review.googlesource.com/427476 --- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index bd82a014c6..9783f38993 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -1073,7 +1073,7 @@ void read_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, Set_NB32_DCT(dev, dct, 0x27c, dword); } else if (lane < 8) { Set_NB32_DCT(dev, dct, 0x274, ~0x0); - Set_NB32_DCT(dev, dct, 0x278, ~(0xff << (lane * 8))); + Set_NB32_DCT(dev, dct, 0x278, ~(0xff << ((lane - 4) * 8))); dword = Get_NB32_DCT(dev, dct, 0x27c); dword |= 0xff; /* EccMask = 0xff */ Set_NB32_DCT(dev, dct, 0x27c, dword); @@ -1170,7 +1170,7 @@ void write_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, Set_NB32_DCT(dev, dct, 0x27c, dword); } else if (lane < 8) { Set_NB32_DCT(dev, dct, 0x274, ~0x0); - Set_NB32_DCT(dev, dct, 0x278, ~(0xff << (lane * 8))); + Set_NB32_DCT(dev, dct, 0x278, ~(0xff << ((lane - 4) * 8))); dword = Get_NB32_DCT(dev, dct, 0x27c); dword |= 0xff; /* EccMask = 0xff */ Set_NB32_DCT(dev, dct, 0x27c, dword);