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UPSTREAM: soc/intel/skylake: Add tsc_freq.c to verstage

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This is required to provide tsc freq required by timer library.

BUG=b:35583330
TEST=Verified that delay(5) in verstage adds a delay of 5 seconds.

Change-Id: I0b513dabd0a3f8ff3e5a52717d70757c709e7f1e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3255839be1
Original-Change-Id: I03edebe394522516b46125fae1a17e9a06fd5f45
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19094
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/471455
This commit is contained in:
Furquan Shaikh 2017-03-31 13:49:31 -07:00 • committed by chrome-bot
parent 045811048c
commit f628623217
1 changed files with 1 additions and 0 deletions
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src/soc/intel/skylake/Makefile.inc
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@ -33,6 +33,7 @@ verstage-$(CONFIG_UART_DEBUG) += uart_debug.c
verstage-y += pmutil.c
verstage-y += bootblock/i2c.c
verstage-y += spi.c
verstage-y += tsc_freq.c
romstage-y += flash_controller.c
romstage-y += gpio.c