From f385338a15c372e5a942a71eb6c8db035f75c4f7 Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Fri, 7 Mar 2008 06:33:05 +0000 Subject: [PATCH] Make cs5536_setup_onchipuart() handle both UARTs and add missing break in dbe61 initram. Signed-off-by: Carl-Daniel Hailfinger Tested on dbe62. I had to run cs5536/stage1.c through indent -kr -i8 because emacs is somehow confused by parts of it. Weird. indent made some parts ugly, at least to my eyes. Oh well. Acked-by: Ronald G. Minnich git-svn-id: svn://coreboot.org/repository/coreboot-v3@638 f3766cd6-281f-0410-b1cd-43a5c92072e9 --- mainboard/amd/norwich/stage1.c | 2 +- mainboard/artecgroup/dbe61/initram.c | 1 + mainboard/artecgroup/dbe61/stage1.c | 2 +- mainboard/artecgroup/dbe62/irq_tables.h | 3 +- mainboard/artecgroup/dbe62/stage1.c | 2 +- southbridge/amd/cs5536/cs5536.h | 3 +- southbridge/amd/cs5536/stage1.c | 39 ++++++++++++++++--------- 7 files changed, 32 insertions(+), 20 deletions(-) diff --git a/mainboard/amd/norwich/stage1.c b/mainboard/amd/norwich/stage1.c index e029e1c37f..8140394a63 100644 --- a/mainboard/amd/norwich/stage1.c +++ b/mainboard/amd/norwich/stage1.c @@ -42,7 +42,7 @@ void hardware_stage1(void) * early MSR setup for the CS5536. We do this early for debug. * Real setup should be done in chipset init via dts settings. */ - cs5536_setup_onchipuart(); + cs5536_setup_onchipuart(1); } void mainboard_pre_payload(void) diff --git a/mainboard/artecgroup/dbe61/initram.c b/mainboard/artecgroup/dbe61/initram.c index 3f2e275842..c81d047967 100644 --- a/mainboard/artecgroup/dbe61/initram.c +++ b/mainboard/artecgroup/dbe61/initram.c @@ -102,6 +102,7 @@ u8 spd_read_byte(u16 device, u8 address) for (i = 0; i < ARRAY_SIZE(spd_table); i++) { if (spd_table[i].address == address) { ret = spd_table[i].data; + break; } } diff --git a/mainboard/artecgroup/dbe61/stage1.c b/mainboard/artecgroup/dbe61/stage1.c index b24d4b9413..c159171b0d 100644 --- a/mainboard/artecgroup/dbe61/stage1.c +++ b/mainboard/artecgroup/dbe61/stage1.c @@ -59,7 +59,7 @@ void hardware_stage1(void) * NOTE: Must do this AFTER the early_setup! It is counting on some * early MSR setup for the CS5536. */ - cs5536_setup_onchipuart(); + cs5536_setup_onchipuart(2); } void mainboard_pre_payload(void) diff --git a/mainboard/artecgroup/dbe62/irq_tables.h b/mainboard/artecgroup/dbe62/irq_tables.h index d82caa1eae..d8d64a60b9 100644 --- a/mainboard/artecgroup/dbe62/irq_tables.h +++ b/mainboard/artecgroup/dbe62/irq_tables.h @@ -20,8 +20,7 @@ #include /* Number of slots and devices in the PIR table */ -#error IRQ_SLOT_COUNT does not match PIR table contents, IRQ routing setup will access uninitialied memory -#define IRQ_SLOT_COUNT 5 +#define IRQ_SLOT_COUNT 3 /* Platform IRQs */ #define PIRQA 10 diff --git a/mainboard/artecgroup/dbe62/stage1.c b/mainboard/artecgroup/dbe62/stage1.c index ea196bed14..45a7c1cca3 100644 --- a/mainboard/artecgroup/dbe62/stage1.c +++ b/mainboard/artecgroup/dbe62/stage1.c @@ -58,7 +58,7 @@ void hardware_stage1(void) * NOTE: Must do this AFTER the early_setup! It is counting on some * early MSR setup for the CS5536. */ - cs5536_setup_onchipuart2(); + cs5536_setup_onchipuart(2); } void mainboard_pre_payload(void) diff --git a/southbridge/amd/cs5536/cs5536.h b/southbridge/amd/cs5536/cs5536.h index 76aa1e15d8..b96c4900e2 100644 --- a/southbridge/amd/cs5536/cs5536.h +++ b/southbridge/amd/cs5536/cs5536.h @@ -443,8 +443,7 @@ /* Function prototypes */ void cs5536_disable_internal_uart(void); -void cs5536_setup_onchipuart(void); -void cs5536_setup_onchipuart2(void); +void cs5536_setup_onchipuart(int uart); void cs5536_stage1(void); #endif /* SOUTHBRIDGE_AMD_CS5536_CS5536_H */ diff --git a/southbridge/amd/cs5536/stage1.c b/southbridge/amd/cs5536/stage1.c index f2ec241cef..7afda12166 100644 --- a/southbridge/amd/cs5536/stage1.c +++ b/southbridge/amd/cs5536/stage1.c @@ -49,10 +49,10 @@ static void cs5536_setup_extmsr(void) /* TODO: unsigned char -> u8? */ #if CS5536_GLINK_PORT_NUM <= 4 msr.lo = CS5536_DEV_NUM << - (unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8); + (unsigned char) ((CS5536_GLINK_PORT_NUM - 1) * 8); #else msr.hi = CS5536_DEV_NUM << - (unsigned char)((CS5536_GLINK_PORT_NUM - 5) * 8); + (unsigned char) ((CS5536_GLINK_PORT_NUM - 5) * 8); #endif wrmsr(GLPCI_ExtMSR, msr); @@ -90,11 +90,11 @@ static void cs5536_usb_swapsif(void) } static const struct msrinit msr_table[] = { - {MDD_LBAR_SMB, {.hi = 0x0000f001, .lo = SMBUS_IO_BASE}}, - {MDD_LBAR_GPIO, {.hi = 0x0000f001, .lo = GPIO_IO_BASE}}, - {MDD_LBAR_MFGPT, {.hi = 0x0000f001, .lo = MFGPT_IO_BASE}}, - {MDD_LBAR_ACPI, {.hi = 0x0000f001, .lo = ACPI_IO_BASE}}, - {MDD_LBAR_PMS, {.hi = 0x0000f001, .lo = PMS_IO_BASE}}, + {MDD_LBAR_SMB, {.hi = 0x0000f001,.lo = SMBUS_IO_BASE}}, + {MDD_LBAR_GPIO, {.hi = 0x0000f001,.lo = GPIO_IO_BASE}}, + {MDD_LBAR_MFGPT, {.hi = 0x0000f001,.lo = MFGPT_IO_BASE}}, + {MDD_LBAR_ACPI, {.hi = 0x0000f001,.lo = ACPI_IO_BASE}}, + {MDD_LBAR_PMS, {.hi = 0x0000f001,.lo = PMS_IO_BASE}}, }; /** @@ -147,15 +147,15 @@ void cs5536_disable_internal_uart(void) * Disable and reset them and configure them later (SIO init). */ msr = rdmsr(MDD_UART1_CONF); - msr.lo = 1; /* Reset */ + msr.lo = 1; /* Reset */ wrmsr(MDD_UART1_CONF, msr); - msr.lo = 0; /* Disable */ + msr.lo = 0; /* Disable */ wrmsr(MDD_UART1_CONF, msr); msr = rdmsr(MDD_UART2_CONF); - msr.lo = 1; /* Reset */ + msr.lo = 1; /* Reset */ wrmsr(MDD_UART2_CONF, msr); - msr.lo = 0; /* Disable */ + msr.lo = 0; /* Disable */ wrmsr(MDD_UART2_CONF, msr); } @@ -182,7 +182,7 @@ static void cs5536_setup_cis_mode(void) * * See page 412 of the AMD Geode CS5536 Companion Device data book. */ -void cs5536_setup_onchipuart(void) +void cs5536_setup_onchipuart1(void) { struct msr msr; @@ -238,7 +238,8 @@ void cs5536_setup_onchipuart2(void) outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT); /* Set: GPIO 3 + 3 Pull Up (0x18) */ - outl(GPIOL_3_SET | GPIOL_4_SET, GPIO_IO_BASE + GPIOL_PULLUP_ENABLE); + outl(GPIOL_3_SET | GPIOL_4_SET, + GPIO_IO_BASE + GPIOL_PULLUP_ENABLE); /* set address to 3F8 */ msr = rdmsr(MDD_LEG_IO); @@ -255,6 +256,18 @@ void cs5536_setup_onchipuart2(void) wrmsr(MDD_UART2_CONF, msr); } +void cs5536_setup_onchipuart(int uart) +{ + switch (uart) { + case 1: + cs5536_setup_onchipuart1(); + break; + case 2: + cs5536_setup_onchipuart2(); + break; + } +} + /** * Board setup.