Emulation/switch-coreboot
1
0
Fork 0
mirror of https://github.com/fail0verflow/switch-coreboot.git synced 2025-05-04 01:39:18 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Added PCI bus parity error checking on data and addresses. Errors cause a NMI.

Browse source
This commit is contained in:
Tom Zimmerman 2003-10-03 15:40:07 +00:00
parent 9648966b58
commit f208fe1e7d
4 changed files with 48 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
src/southbridge/intel/82801ca/Config
View file

@ -9,3 +9,4 @@ object ich3_rtc.o
object ich3_power.o
object ich3_1e0_misc.o
object ich3_1f0_misc.o
object ich3_pci_parity.o

20
src/southbridge/intel/82801ca/ich3_pci_parity.c Normal file
View file

@ -0,0 +1,20 @@
#include <mem.h>
#include <pci.h>
#include <arch/io.h>
#include <printk.h>
#
void ich3_pci_parity_enable(void)
{
uint8_t reg;
/* 2SERREN - SERR enable for bridge control */
/* 2PEREN - Parity error response enable */
pcibios_read_config_byte(0, ((30 << 3) + (0 << 0)), 0x3e, &reg);
reg |= ((1 << 1) + (1 << 0));
pcibios_write_config_byte(0, ((30 << 3) + (0 << 0)), 0x3e, reg);
return;
}

1
src/southbridge/intel/82870/Config
View file

@ -1,2 +1,3 @@
object p64h2_ioapic.o
object p64h2_pcibridge.o
object p64h2_pci_parity.o

26
src/southbridge/intel/82870/p64h2_pci_parity.c Normal file
View file

@ -0,0 +1,26 @@
#include <mem.h>
#include <pci.h>
#include <arch/io.h>
#include <printk.h>
#
void p64h2_pci_parity_enable(void)
{
uint8_t reg;
/* 2SERREN - SERR enable for PCI bridge secondary device */
/* 2PEREN - Parity error for PCI bridge secondary device */
pcibios_read_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, &reg);
reg |= ((1 << 1) + (1 << 0));
pcibios_write_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, reg);
/* 2SERREN - SERR enable for PCI bridge secondary device */
/* 2PEREN - Parity error for PCI bridge secondary device */
pcibios_read_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, &reg);
reg |= ((1 << 1) + (1 << 0));
pcibios_write_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, reg);
return;
}