From f208fe1e7d934d9c349471de53b465eff835ae83 Mon Sep 17 00:00:00 2001
From: Tom Zimmerman <tzimmerman@lnxi.com>
Date: Fri, 3 Oct 2003 15:40:07 +0000
Subject: [PATCH] Added PCI bus parity error checking on data and addresses.
 Errors cause a NMI.

---
 src/southbridge/intel/82801ca/Config          |  1 +
 .../intel/82801ca/ich3_pci_parity.c           | 20 ++++++++++++++
 src/southbridge/intel/82870/Config            |  1 +
 .../intel/82870/p64h2_pci_parity.c            | 26 +++++++++++++++++++
 4 files changed, 48 insertions(+)
 create mode 100644 src/southbridge/intel/82801ca/ich3_pci_parity.c
 create mode 100644 src/southbridge/intel/82870/p64h2_pci_parity.c

diff --git a/src/southbridge/intel/82801ca/Config b/src/southbridge/intel/82801ca/Config
index c6adb65c7d..0c28a391d7 100644
--- a/src/southbridge/intel/82801ca/Config
+++ b/src/southbridge/intel/82801ca/Config
@@ -9,3 +9,4 @@ object ich3_rtc.o
 object ich3_power.o
 object ich3_1e0_misc.o
 object ich3_1f0_misc.o
+object ich3_pci_parity.o
diff --git a/src/southbridge/intel/82801ca/ich3_pci_parity.c b/src/southbridge/intel/82801ca/ich3_pci_parity.c
new file mode 100644
index 0000000000..bd5823941b
--- /dev/null
+++ b/src/southbridge/intel/82801ca/ich3_pci_parity.c
@@ -0,0 +1,20 @@
+#include <mem.h>
+#include <pci.h>
+#include <arch/io.h>
+#include <printk.h>
+#
+
+void ich3_pci_parity_enable(void)
+{
+        uint8_t reg;
+
+        /* 2SERREN - SERR enable for bridge control */
+        /* 2PEREN  - Parity error response enable   */
+        pcibios_read_config_byte(0, ((30 << 3) + (0 << 0)), 0x3e, &reg);
+        reg |= ((1 << 1) + (1 << 0));
+        pcibios_write_config_byte(0, ((30 << 3) + (0 << 0)), 0x3e, reg);
+
+        return;
+}
+
+
diff --git a/src/southbridge/intel/82870/Config b/src/southbridge/intel/82870/Config
index 11686ebad0..8888710080 100644
--- a/src/southbridge/intel/82870/Config
+++ b/src/southbridge/intel/82870/Config
@@ -1,2 +1,3 @@
 object p64h2_ioapic.o
 object p64h2_pcibridge.o
+object p64h2_pci_parity.o
diff --git a/src/southbridge/intel/82870/p64h2_pci_parity.c b/src/southbridge/intel/82870/p64h2_pci_parity.c
new file mode 100644
index 0000000000..d80f9213c9
--- /dev/null
+++ b/src/southbridge/intel/82870/p64h2_pci_parity.c
@@ -0,0 +1,26 @@
+#include <mem.h>
+#include <pci.h>
+#include <arch/io.h>
+#include <printk.h>
+#
+
+void p64h2_pci_parity_enable(void)
+{
+        uint8_t reg;
+
+        /* 2SERREN - SERR enable for PCI bridge secondary device  */
+        /* 2PEREN  - Parity error for PCI bridge secondary device  */
+        pcibios_read_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, &reg);
+        reg |= ((1 << 1) + (1 << 0));
+        pcibios_write_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, reg);
+
+        /* 2SERREN - SERR enable for PCI bridge secondary device  */
+        /* 2PEREN  - Parity error for PCI bridge secondary device  */
+        pcibios_read_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, &reg);
+        reg |= ((1 << 1) + (1 << 0));
+        pcibios_write_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, reg);
+
+        return;
+}
+
+