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UPSTREAM: mainboard/intel/kblrvp: Configure usb over current pin & cdclock

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Configure overcurrent pins for various usb ports.
Configure CdClock to 3.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17251
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I57f1feb7e03c5bc7b125ea7e0735481fee91b6f6
Reviewed-on: https://chromium-review.googlesource.com/408979
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Naresh G Solanki 2016-11-06 14:12:55 +05:30 • committed by chrome-bot
parent 10e5289998
commit e9ce0eae74
1 changed files with 12 additions and 0 deletions
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12
src/mainboard/intel/kblrvp/ramstage.c
View file

@ -18,7 +18,19 @@
void mainboard_silicon_init_params(FSP_SIL_UPD *params)
{
u8 i;
/* Configure pads prior to SiliconInit() in case there's any
* dependencies during hardware initialization. */
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
params->CdClock = 3;
/* Set proper OC for various USB ports*/
u8 usb2_oc[] = { 0x0, 0x2, 0x8, 0x8, 0x2, 0x8, 0x8, 0x8, 0x1, 0x8};
u8 usb3_oc[] = { 0x0, 0x8, 0x8, 0x1, 0x8, 0x8 };
for (i = 0; i < ARRAY_SIZE(usb2_oc); i++)
params->Usb2OverCurrentPin[i] = usb2_oc[i];
for (i = 0; i < ARRAY_SIZE(usb3_oc); i++)
params->Usb3OverCurrentPin[i] = usb3_oc[i];
}