From e9ce0eae746bd93e05593b8b6eb8a355147fead8 Mon Sep 17 00:00:00 2001 From: Naresh G Solanki Date: Sun, 6 Nov 2016 14:12:55 +0530 Subject: [PATCH] UPSTREAM: mainboard/intel/kblrvp: Configure usb over current pin & cdclock Configure overcurrent pins for various usb ports. Configure CdClock to 3. BUG=None BRANCH=None TEST=None Signed-off-by: Naresh G Solanki Reviewed-on: https://review.coreboot.org/17251 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Change-Id: I57f1feb7e03c5bc7b125ea7e0735481fee91b6f6 Reviewed-on: https://chromium-review.googlesource.com/408979 Commit-Ready: Furquan Shaikh Tested-by: Furquan Shaikh Reviewed-by: Aaron Durbin --- src/mainboard/intel/kblrvp/ramstage.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/mainboard/intel/kblrvp/ramstage.c b/src/mainboard/intel/kblrvp/ramstage.c index ed37681822..6a509b7b6d 100644 --- a/src/mainboard/intel/kblrvp/ramstage.c +++ b/src/mainboard/intel/kblrvp/ramstage.c @@ -18,7 +18,19 @@ void mainboard_silicon_init_params(FSP_SIL_UPD *params) { + u8 i; /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + params->CdClock = 3; + + /* Set proper OC for various USB ports*/ + u8 usb2_oc[] = { 0x0, 0x2, 0x8, 0x8, 0x2, 0x8, 0x8, 0x8, 0x1, 0x8}; + u8 usb3_oc[] = { 0x0, 0x8, 0x8, 0x1, 0x8, 0x8 }; + + for (i = 0; i < ARRAY_SIZE(usb2_oc); i++) + params->Usb2OverCurrentPin[i] = usb2_oc[i]; + + for (i = 0; i < ARRAY_SIZE(usb3_oc); i++) + params->Usb3OverCurrentPin[i] = usb3_oc[i]; }