From e8f5fd7970139d56ab7df39795d20b9770248c95 Mon Sep 17 00:00:00 2001 From: Shaunak Saha Date: Fri, 9 Sep 2016 14:50:34 -0700 Subject: [PATCH] UPSTREAM: intel/amenia: Remove setting of GPIO_TIER1_SCI enable bit This patch removes setting of gpio_tier1_sci_en from mainboard smihandler code. Gpio_tier1_sci enable bit is set from gpio.asl now. BUG=chrome-os-partner:56483 BRANCH=None TEST=System resumes from S3 on lidopen, powerbutton and USB wake. Also from S0iX system is resuming for WIFI wake. Signed-off-by: Shaunak Saha Reviewed-on: https://review.coreboot.org/16565 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Paul Menzel Reviewed-by: Andrey Petrov Change-Id: I066f0907a1c597e6fee09821910c59a8a90cccaa Reviewed-on: https://chromium-review.googlesource.com/385901 Commit-Ready: Furquan Shaikh Tested-by: Furquan Shaikh Reviewed-by: Aaron Durbin --- src/mainboard/intel/amenia/smihandler.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/mainboard/intel/amenia/smihandler.c b/src/mainboard/intel/amenia/smihandler.c index 05d363f876..eb5377be30 100644 --- a/src/mainboard/intel/amenia/smihandler.c +++ b/src/mainboard/intel/amenia/smihandler.c @@ -22,9 +22,6 @@ void mainboard_smi_sleep(u8 slp_typ) { - if (slp_typ == ACPI_S3) - enable_gpe(GPIO_TIER_1_SCI); - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS);