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Trivial fixes of printk \r\n and white space.

Browse source 
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@958 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Myles Watson 2008-10-28 17:29:07 +00:00
parent 345f5ac818
commit e7ea68860d
12 changed files with 634 additions and 634 deletions
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186
arch/x86/amd/model_fxx/init_cpus.c
View file

@ -40,10 +40,10 @@
*/
/**
* for_each_ap
* iterate over all APs and have them run a function.
* iterate over all APs and have them run a function.
* The behaviour is modified by the core_range parameter
* @param bsp_apicid The BSP APIC ID number
* @param core_range modifier for the range of cores to run on:
* @param core_range modifier for the range of cores to run on:
* core_range = 0 : all cores
* core range = 1 : core 0 only
* core range = 2 : cores other than core0
@ -54,7 +54,7 @@ void for_each_ap(unsigned bsp_apicid, unsigned core_range,
process_ap_t process_ap, void *gp)
{
/* Assume the OS will not change our APIC ID. Why does this matter? Because some of the setup
* we do for other cores may depend on it not being changed.
* we do for other cores may depend on it not being changed.
*/
unsigned int ap_apicid;
@ -69,12 +69,12 @@ void for_each_ap(unsigned bsp_apicid, unsigned core_range,
nodes = get_nodes();
/* if the get_option fails siblings remain disabled. */
// This sound not be a config option. disable_siblings = !CONFIG_LOGICAL_CPUS;
// This sound not be a config option. disable_siblings = !CONFIG_LOGICAL_CPUS;
//get_option(&disable_siblings, "dual_core");
/* There is an interesting problem in different steppings. See page 373. The interpretation of the
/* There is an interesting problem in different steppings. See page 373. The interpretation of the
* APIC ID bits is different. To determine which order is used, check bit 54 of the programmers' guide
* here we assume that all nodes are the same stepping.
* here we assume that all nodes are the same stepping.
* If not, "otherwise we can use use nb_cfg_54 from bsp for all nodes"
*/
nb_cfg_54 = read_nb_cfg_54();
@ -88,7 +88,7 @@ void for_each_ap(unsigned bsp_apicid, unsigned core_range,
NORTHBRIDGE_CAP) >> NBCAP_CmpCap_SHIFT) &
NBCAP_CmpCap_MASK);
if (nb_cfg_54) {
if (j == 0) // if it is single core, we need to increase siblings for apic calculation
if (j == 0) // if it is single core, we need to increase siblings for apic calculation
j = 1;
}
siblings = j;
@ -133,18 +133,18 @@ void for_each_ap(unsigned bsp_apicid, unsigned core_range,
/**
* lapic remote read
* lapics are more than just an interrupt steering system. They are a key part of inter-processor communication.
* They can be used to start, control, and interrupt other CPUs from the BSP. It is not possible to bring up
* an SMP system without somehow using the APIC.
* CPUs and their attached IOAPICs all have an ID. For convenience, these IDs are unique.
* The communications is packet-based, using (in coreboot) a polling-based strategy. As with most APIC ops,
* the ID is the APIC ID. Even more fun, code can read registers in remote APICs, and this in turn can
* provide us with remote CPU status.
* This function does a remote read given an apic id. It returns the value or an error. It can time out.
* lapics are more than just an interrupt steering system. They are a key part of inter-processor communication.
* They can be used to start, control, and interrupt other CPUs from the BSP. It is not possible to bring up
* an SMP system without somehow using the APIC.
* CPUs and their attached IOAPICs all have an ID. For convenience, these IDs are unique.
* The communications is packet-based, using (in coreboot) a polling-based strategy. As with most APIC ops,
* the ID is the APIC ID. Even more fun, code can read registers in remote APICs, and this in turn can
* provide us with remote CPU status.
* This function does a remote read given an apic id. It returns the value or an error. It can time out.
* @param apicid Remote APIC id
* @param reg The register number to read
* @param pvalue pointer to int for return value
* @returns 0 on success, -1 on error
* @returns 0 on success, -1 on error
*/
int lapic_remote_read(int apicid, int reg, unsigned int *pvalue)
{
@ -153,8 +153,8 @@ int lapic_remote_read(int apicid, int reg, unsigned int *pvalue)
int result;
/* Wait for the idle state. Could we enter this with the APIC busy? It's possible. */
lapic_wait_icr_idle();
/* The APIC Interrupt Control Registers define the operations and destinations.
* In this case, we set ICR2 to the dest, set the op to REMOTE READ, and set the
/* The APIC Interrupt Control Registers define the operations and destinations.
* In this case, we set ICR2 to the dest, set the op to REMOTE READ, and set the
* reg (which is 16-bit aligned, it seems, hence the >> 4
*/
lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
@ -167,7 +167,7 @@ int lapic_remote_read(int apicid, int reg, unsigned int *pvalue)
/* note here the ICR is command and status. */
/* Why don't we use the lapic_wait_icr_idle() above? */
/* That said, it's a bad idea to mess with this code too much.
* APICs (and their code) are quite fragile.
* APICs (and their code) are quite fragile.
*/
status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
} while (status == LAPIC_ICR_BUSY && timeout++ < 1000);
@ -195,16 +195,16 @@ void print_apicid_nodeid_coreid(unsigned apicid, struct node_core_id id,
const char *str)
{
printk(BIOS_DEBUG, "%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\n",
str, apicid, id.nodeid, id.coreid);
str, apicid, id.nodeid, id.coreid);
}
/**
* Using the APIC remote read code, wait for the CPU to enter a given state
* This function can time out.
* This function can time out.
* @param apicid The apicid of the remote CPU
* @param state The state we are waiting for
* @return 0 on success, readback value on error
* @return 0 on success, readback value on error
*/
unsigned int wait_cpu_state(unsigned apicid, unsigned state)
{
@ -229,8 +229,8 @@ unsigned int wait_cpu_state(unsigned apicid, unsigned state)
return timeout;
}
/**
* Wait for an AP to start.
/**
* Wait for an AP to start.
* @param ap_apicid the apic id of the CPu
* @param gp arbitrary parameter
*/
@ -246,30 +246,30 @@ void wait_ap_started(unsigned ap_apicid, void *gp)
}
}
/**
* disable cache as ram on a BSP.
* For reasons not totally known we are saving ecx and edx.
* That will work on k8 as we copy the stack and return in the same stack frame.
/**
* disable cache as ram on a BSP.
* For reasons not totally known we are saving ecx and edx.
* That will work on k8 as we copy the stack and return in the same stack frame.
*/
void disable_cache_as_ram_bsp(void)
{
__asm__ volatile (
// "pushl %eax\n\t"
"pushl %edx\n\t"
"pushl %ecx\n\t"
"pushl %edx\n\t"
"pushl %ecx\n\t"
);
disable_cache_as_ram();
__asm__ volatile (
"popl %ecx\n\t"
"popl %edx\n\t"
// "popl %eax\n\t"
);
__asm__ volatile (
"popl %ecx\n\t"
"popl %edx\n\t"
// "popl %eax\n\t"
);
}
/**
* wait for all apics to start. Make sure we don't wait on ourself.
* wait for all apics to start. Make sure we don't wait on ourself.
* @param bsp_apicid The BSP APIC ID
*/
void wait_all_aps_started(unsigned bsp_apicid)
@ -278,14 +278,14 @@ void wait_all_aps_started(unsigned bsp_apicid)
}
/**
* Wait on all other cores to start. This includes cores on bsp, we think.
* Wait on all other cores to start. This includes cores on bsp, we think.
* @param bsp_apicid The BSP APIC ID
*/
void wait_all_other_cores_started(unsigned bsp_apicid) // all aps other than core0
{
printk(BIOS_DEBUG, "started ap apicid: ");
for_each_ap(bsp_apicid, 2, wait_ap_started, (void *) 0);
printk(BIOS_DEBUG, "\r\n");
printk(BIOS_DEBUG, "\n");
}
void STOP_CAR_AND_CPU(void)
@ -301,49 +301,49 @@ void STOP_CAR_AND_CPU(void)
#if MEM_TRAIN_SEQ == 1
void train_ram_on_node(unsigned nodeid, unsigned coreid,
struct sys_info *sysinfo,
void * retcall);
struct sys_info *sysinfo,
void * retcall);
#endif
/**
* Init all the CPUs. Part of the process involves setting APIC IDs for all cores on all sockets.
* The code that is run
* is for the most part the same on all cpus and cores of cpus.
* Init all the CPUs. Part of the process involves setting APIC IDs for all cores on all sockets.
* The code that is run
* is for the most part the same on all cpus and cores of cpus.
* Since we only support F2 and later Opteron CPUs our job is considerably simplified
* as compared to v2. The basic process it to set up the cpu 0 core 0, then the other cpus, one by one.
* Complications: BSP, a.k.a. cpu 0, comes up with APIC id 0, the others all come up with APIC id 7,
* including other cpu 0 cores. Why? Because the BSP brings them up one by one and assigns their APIC ID.
* There is also the question of the need to "lift" the BSP APIC id.
* For some setups, we want the BSP APIC id to be 0; for others,
* a non-zero value is preferred. This means that we have to change the BSP APIC ID on the fly.
*
* So here we have it, some of the slickest code you'll ever read. Which cores run this function?
* All of them.
* as compared to v2. The basic process it to set up the cpu 0 core 0, then the other cpus, one by one.
* Complications: BSP, a.k.a. cpu 0, comes up with APIC id 0, the others all come up with APIC id 7,
* including other cpu 0 cores. Why? Because the BSP brings them up one by one and assigns their APIC ID.
* There is also the question of the need to "lift" the BSP APIC id.
* For some setups, we want the BSP APIC id to be 0; for others,
* a non-zero value is preferred. This means that we have to change the BSP APIC ID on the fly.
*
* So here we have it, some of the slickest code you'll ever read. Which cores run this function?
* All of them.
* Do they communicate through APIC Interrupts or memory? Yes. Both. APICs before
* memory is ready, memory afterword. What is the state of the cores at the end of this function?
* They are all ready to go, just waiting to be started up. What is the state of memory on all sockets?
* It's all working.
* Except that it's not quite that simple. We'll try to comment this well enough to make sense.
* memory is ready, memory afterword. What is the state of the cores at the end of this function?
* They are all ready to go, just waiting to be started up. What is the state of memory on all sockets?
* It's all working.
* Except that it's not quite that simple. We'll try to comment this well enough to make sense.
* But rest assured, it's complicated!
* @param cpu_init_detectedx has this cpu been init'ed before?
* @param sysinfo The sys_info pointer
* @param cpu_init_detectedx has this cpu been init'ed before?
* @param sysinfo The sys_info pointer
* @returns the BSP APIC ID
*/
unsigned int init_cpus(unsigned cpu_init_detectedx,
struct sys_info *sysinfo)
struct sys_info *sysinfo)
{
unsigned bsp_apicid = 0;
unsigned apicid;
struct node_core_id id;
/* this is a bit weird but soft_reset can be defined in many places,
* so finding a common
/* this is a bit weird but soft_reset can be defined in many places,
* so finding a common
* include file to use is a little daunting.
*/
void soft_reset(void);
#warning ignore init_detectedx
cpu_init_detectedx = 0;
/*
/*
* MTRR must be set by this point.
*/
@ -352,19 +352,19 @@ cpu_init_detectedx = 0;
id = get_node_core_id();
printk(BIOS_DEBUG, "init_cpus: node %d core %d\n", id.nodeid, id.coreid);
/* The NB_CFG MSR is shared between cores on a given node.
* Here is an interesting parallel processing bug: if you were to start the
/* The NB_CFG MSR is shared between cores on a given node.
* Here is an interesting parallel processing bug: if you were to start the
* other cores and THEN make this setting, different cores might read
* a different value! Since ALL cores run this code, it is very important to have
* core0 initialize this setting before any others.
* So do this setting very early in the function to make sure the bit has a
* consistent value on all cores.
* So do this setting very early in the function to make sure the bit has a
* consistent value on all cores.
*/
if (id.coreid == 0) {
set_apicid_cpuid_lo(); /* only set it on core0 */
/* Should we enable extended APIC IDs? This feature is used on a number of mainboards.
* It is required when the board requires more than 4 bits of ID.
* the question is, why not use it on all of them? Would it do harm to always enable it?
/* Should we enable extended APIC IDs? This feature is used on a number of mainboards.
* It is required when the board requires more than 4 bits of ID.
* the question is, why not use it on all of them? Would it do harm to always enable it?
*/
#if ENABLE_APIC_EXT_ID == 1
enable_apic_ext_id(id.nodeid);
@ -373,18 +373,18 @@ cpu_init_detectedx = 0;
/* enable the local APIC, which we need to do message passing between sockets. */
enable_lapic();
// init_timer(); // We need TMICT to pass msg for FID/VID change
// init_timer(); // We need TMICT to pass msg for FID/VID change
#if (ENABLE_APIC_EXT_ID == 1)
/* we wish to enable extended APIC IDs. We have an APIC ID already which we can
* use as a "base" for the extended ID.
* use as a "base" for the extended ID.
*/
unsigned initial_apicid = get_initial_apicid();
/* We don't always need to lift the BSP APIC ID.
* Again, is there harm if we do it anyway?
/* We don't always need to lift the BSP APIC ID.
* Again, is there harm if we do it anyway?
*/
#if LIFT_BSP_APIC_ID == 0
if (initial_apicid != 0) // This CPU is not the BSP so lift it.
if (initial_apicid != 0) // This CPU is not the BSP so lift it.
#endif
{
/* Use the CPUs initial 4-bit APIC id as the basis for the extended ID */
@ -395,7 +395,7 @@ cpu_init_detectedx = 0;
lapic_write(LAPIC_ID, dword);
}
/* Again, the bsp_apicid is a special case and if we changed it
/* Again, the bsp_apicid is a special case and if we changed it
* we need to remember that change.
*/
#if LIFT_BSP_APIC_ID == 1
@ -422,26 +422,26 @@ cpu_init_detectedx = 0;
if (cpu_init_detectedx) {
print_apicid_nodeid_coreid(apicid, id,
"\r\n\r\n\r\nINIT detected from ");
printk(BIOS_DEBUG, "\r\nIssuing SOFT_RESET...\r\n");
"\n\n\nINIT detected from ");
printk(BIOS_DEBUG, "\nIssuing SOFT_RESET...\n");
soft_reset();
}
if (id.coreid == 0) {
/* not known what this is yet. */
distinguish_cpu_resets(id.nodeid);
// start_other_core(id.nodeid); // start second core in first cpu, only allowed for nb_cfg_54 is not set
// start_other_core(id.nodeid); // start second core in first cpu, only allowed for nb_cfg_54 is not set
}
//Indicate to other CPUs that our CPU is running.
//Indicate to other CPUs that our CPU is running.
/* and, again, recall that this is running on all sockets at some point, although it runs at
* different times.
* different times.
*/
lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x33);
/* non-BSP CPUs are now set up and need to halt. There are a few possibilities here.
* BSP may train memory
* AP may train memory
* In v2, both are possible.
* In v2, both are possible.
*/
if (apicid != bsp_apicid) {
unsigned timeout = 1;
@ -454,13 +454,13 @@ cpu_init_detectedx = 0;
#endif
// We need to stop the CACHE as RAM for this CPU, really?
/* Yes we do. What happens here is really interesting. To this point
* we have used APICs to communicate. We're going to use the sysinfo
* struct. But to do that we have to use real memory. So we have to
* disable car, and do it in a way that lets us continue in this function.
* The way we do it for non-node 0 is to never return from this function,
* but to do the work in this function to train RAM.
* Note that serengeti, the SimNow target, does not do this; it lets BSP train AP memory.
/* Yes we do. What happens here is really interesting. To this point
* we have used APICs to communicate. We're going to use the sysinfo
* struct. But to do that we have to use real memory. So we have to
* disable car, and do it in a way that lets us continue in this function.
* The way we do it for non-node 0 is to never return from this function,
* but to do the work in this function to train RAM.
* Note that serengeti, the SimNow target, does not do this; it lets BSP train AP memory.
*/
/* Wait for the bsp to enter state 44. */
while (timeout && (loop-- > 0)) {
@ -468,10 +468,10 @@ cpu_init_detectedx = 0;
}
if (timeout) {
printk(BIOS_DEBUG, "while waiting for BSP signal to STOP, timeout in ap 0x%08x\n",
apicid);
apicid);
}
/* indicate that we are in state 44 as well. We are catching up to the BSP. */
// old comment follows -- not sure what this means yet.
// old comment follows -- not sure what this means yet.
// bsp can not check it before stop_this_cpu
lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x44);
/* Now set up so we can use RAM. This will be low memory, i.e. BSP memory, already working. */
@ -490,7 +490,7 @@ cpu_init_detectedx = 0;
/**
* Given a node, find out if core0 is started.
* Given a node, find out if core0 is started.
* @param nodeid the node ID
* @returns non-zero if node is started
*/
@ -505,7 +505,7 @@ static unsigned int is_core0_started(unsigned nodeid)
}
/**
* Wait for all core 0s on all CPUs to start up.
* Wait for all core 0s on all CPUs to start up.
*/
void wait_all_core0_started(void)
{
@ -523,6 +523,6 @@ void wait_all_core0_started(void)
}
printk(BIOS_DEBUG, "%s%02x", " ", i);
}
printk(BIOS_DEBUG, "\r\n");
printk(BIOS_DEBUG, "\n");
}

48
mainboard/amd/dbm690t/initram.c
View file

@ -43,15 +43,15 @@
#define DIMM1 0x51
/* this code is very mainboard dependent, sadly. */
/**
/**
* no op at present
*/
static void memreset_setup(void)
{
}
/**
* this is a no op on this platform.
/**
* this is a no op on this platform.
*/
void memreset(int controllers, const struct mem_controller *ctrl)
{
@ -62,10 +62,10 @@ void activate_spd_rom(const struct mem_controller *ctrl)
}
/**
* read a byte from spd.
* read a byte from spd.
* @param device device to read from
* @param address address in the spd ROM
* @return the value of the byte at that address.
* @return the value of the byte at that address.
*/
u8 spd_read_byte(u16 device, u8 address)
{
@ -73,25 +73,25 @@ u8 spd_read_byte(u16 device, u8 address)
return do_smbus_read_byte(device, address);
}
/**
/**
* main for initram for the AMD DBM690T
* @param init_detected Used to indicate that we have been started via init
* @returns 0 on success
* The purpose of this code is to not only get ram going, but get any other cpus/cores going.
* The purpose of this code is to not only get ram going, but get any other cpus/cores going.
* The two activities are very tightly connected and not really seperable.
*
*
*/
/*
* init_detected is used to determine if we did a soft reset as required by a reprogramming of the
* hypertransport links. If we did this kind of reset, bit 11 will be set in the MTRRdefType_MSR MSR.
* That may seem crazy, but there are not lots of places to hide a bit when the CPU does a reset.
* This value is picked up in assembly, or it should be.
/*
* init_detected is used to determine if we did a soft reset as required by a reprogramming of the
* hypertransport links. If we did this kind of reset, bit 11 will be set in the MTRRdefType_MSR MSR.
* That may seem crazy, but there are not lots of places to hide a bit when the CPU does a reset.
* This value is picked up in assembly, or it should be.
*/
int main(void)
{
/* sure, we could put this in a .h. It's called precisely once, from this one
* place. And it only relates to the initram stage. I think I'll leave it here.
* That way we can see the definition without grepping the source tree.
/* sure, we could put this in a .h. It's called precisely once, from this one
* place. And it only relates to the initram stage. I think I'll leave it here.
* That way we can see the definition without grepping the source tree.
*/
// void do_enable_smbus(void);
void enable_fid_change_on_sb(u16 sbbusn, u16 sbdn);
@ -122,12 +122,12 @@ int main(void)
sysinfo = &(global_vars()->sys_info);
init_detected = cpu_init_detected(me.nodeid);
printk(BIOS_DEBUG, "init_detected: %d\n", init_detected);
/* well, here we are. For starters, we need to know if this is cpu0 core0.
* cpu0 core 0 will do all the DRAM setup.
/* well, here we are. For starters, we need to know if this is cpu0 core0.
* cpu0 core 0 will do all the DRAM setup.
*/
bsp_apicid = init_cpus(init_detected, sysinfo);
// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE);
// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE);
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 0));
@ -141,9 +141,9 @@ int main(void)
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
* (there may be apic id conflicts in that case)
* (there may be apic id conflicts in that case)
*/
start_all_cores();
wait_all_other_cores_started(bsp_apicid);
@ -176,7 +176,7 @@ int main(void)
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
printk(BIOS_INFO, "ht reset -\r\n");
printk(BIOS_INFO, "ht reset -\n");
// soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
soft_reset();
}
@ -192,7 +192,7 @@ int main(void)
//do we need apci timer, tsc...., only debug need it for better output
/* all ap stopped? */
// init_timer(); // Need to use TMICT to synconize FID/VID
// init_timer(); // Need to use TMICT to synconize FID/VID
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
@ -201,7 +201,7 @@ int main(void)
#endif
#if 0
// dump_pci_devices();
// dump_pci_devices();
dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
#endif

60
mainboard/amd/serengeti/initram.c
View file

@ -52,19 +52,19 @@
#define DIMM7 0x57
/* this code is very mainboard dependent, sadly. */
/**
* call the amd 8111 memreset_setup_amd8111 function to jam the GPIOs to reset memory.
/**
* call the amd 8111 memreset_setup_amd8111 function to jam the GPIOs to reset memory.
*/
static void memreset_setup(void)
{
void memreset_setup_amd8111(u8 data, u16 offset);
//GPIO on amd8111 to enable MEMRST ????
memreset_setup_amd8111((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), 0xc0 + 16); //REVC_MEMRST_EN=1
memreset_setup_amd8111((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), 0xc0 + 17);
memreset_setup_amd8111((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), 0xc0 + 16); //REVC_MEMRST_EN=1
memreset_setup_amd8111((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), 0xc0 + 17);
}
/**
* this is a no op on this platform.
/**
* this is a no op on this platform.
*/
void memreset(int controllers, const struct mem_controller *ctrl)
{
@ -86,10 +86,10 @@ void activate_spd_rom(const struct mem_controller *ctrl)
}
/**
* read a byte from spd.
* read a byte from spd.
* @param device device to read from
* @param address address in the spd ROM
* @return the value of the byte at that address.
* @return the value of the byte at that address.
*/
u8 spd_read_byte(u16 device, u8 address)
{
@ -97,30 +97,30 @@ u8 spd_read_byte(u16 device, u8 address)
return smbus_read_byte(device, address);
}
/**
/**
* main for initram for the AMD Serengeti
* init_detected Used to indicate that we have been started via init
* The purpose of this code is to not only get ram going, but get any other cpus/cores going.
* The two activities are very tightly connected and not really seperable.
* The purpose of this code is to not only get ram going, but get any other cpus/cores going.
* The two activities are very tightly connected and not really seperable.
* The BSP (boot strap processor) Core 0 (BSC) is responsible for all training or all sockets. Note that
* this need not be socket 0; one great strength of coreboot, as opposed to other BIOSes, is that it could
* always boot with with a CPU in any socket, and even with empty sockets (as opposed to, e.g., the BIOS
* that came installed on the Sun Ultra 40, which would freeze if one CPU were not installed).
* The bringup proceeds in several sections. The cool part is that this code is run by all CPUs, and
* control flow is managed by seeing which CPU we are -- BSP or AP?
*
* init_detected is used to determine if we did a soft reset as required by a reprogramming of the
* hypertransport links. If we did this kind of reset, bit 11 will be set in the MTRRdefType_MSR MSR.
* That may seem crazy, but there are not lots of places to hide a bit when the CPU does a reset.
* This value is picked up in assembly, or it should be.
* control flow is managed by seeing which CPU we are -- BSP or AP?
*
* init_detected is used to determine if we did a soft reset as required by a reprogramming of the
* hypertransport links. If we did this kind of reset, bit 11 will be set in the MTRRdefType_MSR MSR.
* That may seem crazy, but there are not lots of places to hide a bit when the CPU does a reset.
* This value is picked up in assembly, or it should be.
*
* @return 0 on success
*/
int main(void)
{
/* sure, we could put this in a .h. It's called precisely once, from this one
* place. And it only relates to the initram stage. I think I'll leave it here.
* That way we can see the definition without grepping the source tree.
/* sure, we could put this in a .h. It's called precisely once, from this one
* place. And it only relates to the initram stage. I think I'll leave it here.
* That way we can see the definition without grepping the source tree.
*/
void enable_smbus(void);
void enable_fid_change_on_sb(u16 sbbusn, u16 sbdn);
@ -161,12 +161,12 @@ int main(void)
init_detected = cpu_init_detected(me.nodeid);
printk(BIOS_DEBUG, "init_detected: %d\n", init_detected);
/* well, here we are. For starters, we need to know if this is cpu0 core0.
* cpu0 core 0 will do all the DRAM setup.
/* well, here we are. For starters, we need to know if this is cpu0 core0.
* cpu0 core 0 will do all the DRAM setup.
*/
bsp_apicid = init_cpus(init_detected, sysinfo);
// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE);
// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE);
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 0));
@ -176,16 +176,16 @@ int main(void)
printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
#if MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
#endif
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
* (there may be apic id conflicts in that case)
* (there may be apic id conflicts in that case)
*/
start_all_cores();
wait_all_other_cores_started(bsp_apicid);
@ -195,7 +195,7 @@ int main(void)
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if 0
//it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
//if your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
#endif
@ -220,7 +220,7 @@ int main(void)
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
printk(BIOS_INFO, "ht reset -\r\n");
printk(BIOS_INFO, "ht reset -\n");
soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
}
#endif
@ -235,7 +235,7 @@ int main(void)
//do we need apci timer, tsc...., only debug need it for better output
/* all ap stopped? */
// init_timer(); // Need to use TMICT to synconize FID/VID
// init_timer(); // Need to use TMICT to synconize FID/VID
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
@ -244,7 +244,7 @@ int main(void)
#endif
#if 0
// dump_pci_devices();
// dump_pci_devices();
dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
#endif

2
northbridge/amd/geodelx/raminit.c
View file

@ -84,7 +84,7 @@ void dumplxmsrs(void)
*/
void hcf(void)
{
printk(BIOS_EMERG, "DIE\r\n");
printk(BIOS_EMERG, "DIE\n");
/* This guarantees we flush the UART FIFOs (if any) and also ensures
* that things, in general, keep going so no debug output is lost.

784
northbridge/amd/k8/coherent_ht.c
View file

File diff suppressed because it is too large Load diff

2
northbridge/amd/k8/cpu.c
View file

@ -148,7 +148,7 @@ static unsigned int cpu_bus_scan(struct device * dev, unsigned int max)
e0_later_single_core = 0;
}
if(e0_later_single_core) {
printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\r\n");
printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\n");
j=1;
}

26
southbridge/amd/amd8111/stage1_smbus.c
View file

@ -42,7 +42,7 @@ void enable_smbus(void)
/* Yes, the ACPI device controls the SMBUS. */
if (!pci_conf1_find_on_bus(0, PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ACPI, &dev)){
die("SMBUS controller not found\r\n");
die("SMBUS controller not found\n");
}
pci_conf1_write_config32(dev, 0x58, SMBUS_IO_BASE | 1);
@ -56,7 +56,7 @@ void enable_smbus(void)
/* clear any lingering errors, so the transaction will run */
outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS);
printk(BIOS_SPEW, "SMBus controller enabled\r\n");
printk(BIOS_SPEW, "SMBus controller enabled\n");
}
int smbus_wait_until_ready(u16 smbus_io_base)
@ -71,7 +71,7 @@ int smbus_wait_until_ready(u16 smbus_io_base)
break;
}
if(loops == (SMBUS_TIMEOUT / 2)) {
outw(inw(smbus_io_base + SMBGSTATUS),
outw(inw(smbus_io_base + SMBGSTATUS),
smbus_io_base + SMBGSTATUS);
}
} while(--loops);
@ -85,7 +85,7 @@ int smbus_wait_until_done(u16 smbus_io_base)
do {
u16 val;
smbus_delay();
val = inw(smbus_io_base + SMBGSTATUS);
if (((val & 0x8) == 0) | ((val & 0x0037) != 0)) {
break;
@ -102,7 +102,7 @@ int do_smbus_recv_byte(u16 smbus_io_base, u16 device)
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
}
/* setup transaction */
/* disable interrupts */
outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
@ -147,7 +147,7 @@ int do_smbus_send_byte(u16 smbus_io_base, u16 device, u16 value)
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
}
/* setup transaction */
/* disable interrupts */
outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
@ -190,7 +190,7 @@ int do_smbus_read_byte(u16 smbus_io_base, u16 device, u8 address)
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
}
/* setup transaction */
/* disable interrupts */
outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL);
@ -302,18 +302,18 @@ int smbus_write_byte(u16 device, u16 address, u8 val)
*/
u8 spd_read_byte(u16 device, u8 address)
{
return smbus_read_byte(device, address);
return smbus_read_byte(device, address);
}
/**
* memreset_setup_amd8111
* This function is part of a complex dance played between the mainboard and
* the southbridge. We don't want to export SMBUS_IO_BASE, but neither can the
* amd8111 know about what GPIOs connect to what reset lines. So
* This function is part of a complex dance played between the mainboard and
* the southbridge. We don't want to export SMBUS_IO_BASE, but neither can the
* amd8111 know about what GPIOs connect to what reset lines. So
* we split the difference. The mainboard must call this function with bytes
* to be output to accomplish reset, as well as the offset from IOBASE;
* amd8111 will output those bytes to SMBIOS_IOBASE.
* The caller of this function must have called spd_init for it to work correctly.
* amd8111 will output those bytes to SMBIOS_IOBASE.
* The caller of this function must have called spd_init for it to work correctly.
*/
void memreset_setup_amd8111(u8 data, u16 offset)
{

18
southbridge/amd/sb600/stage1.c
View file

@ -69,7 +69,7 @@ static u8 get_sb600_revision(void)
{
u32 dev;
if (!pci_conf1_find_device(PCI_VENDOR_ID_ATI, 0x4385, &dev)){
die("SMBUS controller not found\r\n");
die("SMBUS controller not found\n");
}
return pci_conf1_read_config8(dev, 0x08);
}
@ -277,10 +277,10 @@ static void sb600_devices_por_init(void)
/* SMBus Device, BDF:0-20-0 */
printk(BIOS_INFO, "sb600_devices_por_init(): SMBus Device, BDF:0-20-0\n");
if (!pci_conf1_find_device(PCI_VENDOR_ID_ATI, 0x4385, &dev)){
die("SMBUS controller not found\r\n");
die("SMBUS controller not found\n");
}
printk(BIOS_INFO, "SMBus controller enabled, sb revision is 0x%x\r\n",
get_sb600_revision());
printk(BIOS_INFO, "SMBus controller enabled, sb revision is 0x%x\n",
get_sb600_revision());
/* sbPorAtStartOfTblCfg */
/* Set A-Link bridge access address. This address is set at device 14h, function 0, register 0xf0.
@ -392,7 +392,7 @@ static void sb600_devices_por_init(void)
byte |= ((1 << 1) + (1 << 6)); /*0x42, save the configuraion for port 0x80. */
pci_conf1_write_config8(dev, 0x4A, byte);
/* Set LPC ROM size, it has been done in sb600_lpc_init().
/* Set LPC ROM size, it has been done in sb600_lpc_init().
* enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB;
* enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB
* pci_conf1_write_config16(dev, 0x68, 0x000e)
@ -401,8 +401,8 @@ static void sb600_devices_por_init(void)
/* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */
pci_conf1_write_config8(dev, 0x7C, 0x05);
/* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM,
* TODO: I don't know what are their mean? */
/* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM,
* TODO: I don't know what these mean? */
printk(BIOS_INFO, "sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n");
pci_conf1_find_device(PCI_VENDOR_ID_ATI, 0x4384, &dev);
/* I don't know why CIM tried to write into a read-only reg! */
@ -416,7 +416,7 @@ static void sb600_devices_por_init(void)
pci_conf1_write_config8(dev, 0x40, 0x26);
/* I don't know why CIM set reg0x1c as 0x11.
/* I don't know why CIM set reg0x1c as 0x11.
* System will block at sdram_initialize() if I set it before call sdram_initialize().
* If it is necessary to set reg0x1c as 0x11, please call this function after sdram_initialize().
* pci_conf1_write_config8(dev, 0x1c, 0x11);
@ -569,7 +569,7 @@ static void sb600_pci_cfg(void)
byte |= (1 << 3);
pci_conf1_write_config8(dev, 0x41, byte);
/* Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles)
/* Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles)
* generated PCIRST#. */
byte = pm_ioread(0x65);
byte |= (1 << 4);

2
southbridge/nvidia/mcp55/stage1.c
View file

@ -436,7 +436,7 @@ unsigned int get_sbdn(unsigned int bus)
*/
u32 bdf;
if (!pci_conf1_find_device(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP55_HT, &bdf)) {
die("PCI_DEVICE_ID_NVIDIA_MCP55_HT not found\r\n");
die("PCI_DEVICE_ID_NVIDIA_MCP55_HT not found\n");
}
return (bdf>>15) & 0x1f;

4
southbridge/nvidia/mcp55/stage1_smbus.c
View file

@ -192,7 +192,7 @@ void enable_smbus(void)
{
u32 bdf;
if (!pci_conf1_find_device(0x10de, 0x0368, &bdf)) {
die("SMBUS controller not found\r\n");
die("SMBUS controller not found\n");
}
printk(BIOS_DEBUG, "SMBus controller enabled\n");
@ -261,6 +261,6 @@ u8 smbusx_write_byte(u8 smb_index, u8 device, u8 address, u8 val)
*/
u8 spd_read_byte(u16 device, u8 address)
{
return smbus_read_byte(device, address);
return smbus_read_byte(device, address);
}

10
superio/ite/it8716f/superio.c
View file

@ -74,14 +74,14 @@ static void init_ec(u16 base)
/* Read out current value of FAN_CTL control register (0x14). */
value = pnp_read_index(base, 0x14);
printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, read value = 0x%02x\r\n",
base + 0x14, value);
printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, read value = 0x%02x\n",
base + 0x14, value);
/* Set FAN_CTL control register (0x14) polarity to high, and
activate fans 1, 2 and 3. */
* activate fans 1, 2 and 3. */
pnp_write_index(base, 0x14, value | 0x87);
printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, writing value = 0x%02x\r\n",
base + 0x14, value | 0x87);
printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, writing value = 0x%02x\n",
base + 0x14, value | 0x87);
}
#endif

126
superio/winbond/w83627hf/superio.c
View file

@ -34,28 +34,28 @@
#include <statictree.h>
#include "w83627hf.h"
static void pnp_enter_ext_func_mode(struct device * dev)
static void pnp_enter_ext_func_mode(struct device * dev)
{
outb(0x87, dev->path.pnp.port);
outb(0x87, dev->path.pnp.port);
outb(0x87, dev->path.pnp.port);
outb(0x87, dev->path.pnp.port);
}
static void pnp_exit_ext_func_mode(struct device * dev)
static void pnp_exit_ext_func_mode(struct device * dev)
{
outb(0xaa, dev->path.pnp.port);
outb(0xaa, dev->path.pnp.port);
}
static void pnp_write_index(u16 port_base, u8 reg, u8 value)
{
outb(reg, port_base);
outb(value, port_base + 1);
outb(reg, port_base);
outb(value, port_base + 1);
}
static u8 pnp_read_index(u16 port_base, u8 reg)
{
outb(reg, port_base);
return inb(port_base + 1);
}
outb(reg, port_base);
return inb(port_base + 1);
}
static void enable_hwm_smbus(struct device * dev) {
/* set the pin 91,92 as I2C bus */
@ -73,14 +73,14 @@ static void init_acpi(struct device * dev)
#warning Fix CMOS handling
// get_option(&power_on, "power_on_after_fail");
pnp_enter_ext_func_mode(dev);
pnp_write_index(dev->path.pnp.port,7,0x0a);
pnp_write_index(dev->path.pnp.port,7,0x0a);
value = pnp_read_config(dev, 0xE4);
value &= ~(3<<5);
if(power_on) {
value |= (1<<5);
}
pnp_write_config(dev, 0xE4, value);
pnp_exit_ext_func_mode(dev);
pnp_exit_ext_func_mode(dev);
}
static void init_hwm(u16 base)
@ -90,24 +90,24 @@ static void init_hwm(u16 base)
unsigned hwm_reg_values[] = {
/* reg, mask, data */
0x40, 0xff, 0x81, /* start HWM */
0x48, 0xaa, 0x2a, /* set SMBus base to 0x54>>1 */
0x4a, 0x21, 0x21, /* set T2 SMBus base to 0x92>>1 and T3 SMBus base to 0x94>>1 */
0x4e, 0x80, 0x00,
0x43, 0x00, 0xff,
0x44, 0x00, 0x3f,
0x4c, 0xbf, 0x18,
0x4d, 0xff, 0x80 /* turn off beep */
0x40, 0xff, 0x81, /* start HWM */
0x48, 0xaa, 0x2a, /* set SMBus base to 0x54>>1 */
0x4a, 0x21, 0x21, /* set T2 SMBus base to 0x92>>1 and T3 SMBus base to 0x94>>1 */
0x4e, 0x80, 0x00,
0x43, 0x00, 0xff,
0x44, 0x00, 0x3f,
0x4c, 0xbf, 0x18,
0x4d, 0xff, 0x80 /* turn off beep */
};
for (i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) {
reg = hwm_reg_values[i];
value = pnp_read_index(base, reg);
for (i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) {
reg = hwm_reg_values[i];
value = pnp_read_index(base, reg);
value &= 0xff & hwm_reg_values[i+1];
value |= 0xff & hwm_reg_values[i+2];
printk(BIOS_SPEW, "base = 0x%04x, reg = 0x%02x, value = 0x%02x\r\n", base, reg,value);
printk(BIOS_SPEW, "base = 0x%04x, reg = 0x%02x, value = 0x%02x\n", base, reg,value);
pnp_write_index(base, reg, value);
}
@ -129,7 +129,7 @@ static void w83627hf_init(struct device * dev)
conf = dev->device_configuration;
switch(dev->path.pnp.device) {
case W83627HF_SP1:
case W83627HF_SP1:
res0 = find_resource(dev, PNP_IDX_IO0);
#warning init_uart8250
//init_uart8250(res0->base, &conf->com1);
@ -144,55 +144,55 @@ static void w83627hf_init(struct device * dev)
res1 = find_resource(dev, PNP_IDX_IO1);
init_pc_keyboard(res0->base, res1->base, &keyboard);
break;
case W83627HF_HWM:
res0 = find_resource(dev, PNP_IDX_IO0);
case W83627HF_HWM:
res0 = find_resource(dev, PNP_IDX_IO0);
#define HWM_INDEX_PORT 5
init_hwm(res0->base + HWM_INDEX_PORT);
break;
case W83627HF_ACPI:
init_acpi(dev);
break;
init_hwm(res0->base + HWM_INDEX_PORT);
break;
case W83627HF_ACPI:
init_acpi(dev);
break;
}
}
void w83627hf_pnp_set_resources(struct device * dev)
{
pnp_enter_ext_func_mode(dev);
pnp_enter_ext_func_mode(dev);
pnp_set_resources(dev);
pnp_exit_ext_func_mode(dev);
}
pnp_exit_ext_func_mode(dev);
}
void w83627hf_pnp_enable_resources(struct device * dev)
{
pnp_enter_ext_func_mode(dev);
pnp_enable_resources(dev);
switch(dev->path.pnp.device) {
{
pnp_enter_ext_func_mode(dev);
pnp_enable_resources(dev);
switch(dev->path.pnp.device) {
case W83627HF_HWM:
printk(BIOS_DEBUG, "w83627hf hwm smbus enabled\n");
enable_hwm_smbus(dev);
break;
}
pnp_exit_ext_func_mode(dev);
pnp_exit_ext_func_mode(dev);
}
void w83627hf_pnp_enable(struct device * dev)
{
if (!dev->enabled) {
pnp_enter_ext_func_mode(dev);
if (!dev->enabled) {
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_exit_ext_func_mode(dev);
}
pnp_exit_ext_func_mode(dev);
}
}
static void phase3_chip_setup_dev(struct device *dev);
struct device_operations w83627hf_ops = {
.phase3_chip_setup_dev = phase3_chip_setup_dev,
.phase3_enable = w83627hf_pnp_enable_resources,
.phase3_chip_setup_dev = phase3_chip_setup_dev,
.phase3_enable = w83627hf_pnp_enable_resources,
.phase4_read_resources = pnp_read_resources,
.phase4_set_resources = w83627hf_pnp_set_resources,
.phase5_enable_resources = w83627hf_pnp_enable,
@ -200,18 +200,18 @@ struct device_operations w83627hf_ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &w83627hf_ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
{ &w83627hf_ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
{ &w83627hf_ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &w83627hf_ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
// No 4 { 0,},
{ &w83627hf_ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
{ &w83627hf_ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &w83627hf_ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, },
{ &w83627hf_ops, W83627HF_GPIO2, },
{ &w83627hf_ops, W83627HF_GPIO3, },
{ &w83627hf_ops, W83627HF_ACPI, },
{ &w83627hf_ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
{ &w83627hf_ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
{ &w83627hf_ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
{ &w83627hf_ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &w83627hf_ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
// No 4 { 0,},
{ &w83627hf_ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
{ &w83627hf_ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &w83627hf_ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, },
{ &w83627hf_ops, W83627HF_GPIO2, },
{ &w83627hf_ops, W83627HF_GPIO3, },
{ &w83627hf_ops, W83627HF_ACPI, },
{ &w83627hf_ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
};