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UPSTREAM: tegra210: Remove fake cpu_reset()

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The Tegra210 SoC never had a proper cpu_reset() implementation, so it's
pointless to pretend there is one. Most ARM SoCs/boards only define
hard_reset() at the moment anyway, so let's stick with that.

BUG=none
BRANCH=none
TEST=none

Change-Id: Ifeb6b0b2a4417bdb13908ceb0aa4e382b40a91c5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c25b2a18fa
Original-Change-Id: I40f39921fa99d6dfabf818e7abe7a5732341cf4f
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19786
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/521025
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Julius Werner 2017-04-14 15:39:23 -07:00 • committed by chrome-bot
parent 2a9d068721
commit e6711e269a
4 changed files with 4 additions and 32 deletions
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4
src/mainboard/google/foster/pmic.c
View file

@ -43,8 +43,8 @@ static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int delay)
if (i2c_writeb(bus, MAX77620_I2C_ADDR, reg, val)) {
printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n",
__func__, reg, val);
/* Reset the SoC on any PMIC write error */
cpu_reset();
/* Reset the board on any PMIC write error */
hard_reset();
} else {
if (delay)
udelay(500);

4
src/mainboard/google/smaug/pmic.c
View file

@ -46,8 +46,8 @@ static void pmic_write_reg(unsigned bus, uint8_t chip, uint8_t reg, uint8_t val,
if (i2c_writeb(bus, chip, reg, val)) {
printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n",
__func__, reg, val);
/* Reset the SoC on any PMIC write error */
cpu_reset();
/* Reset the board on any PMIC write error */
hard_reset();
} else {
if (delay)
udelay(500);

3
src/soc/nvidia/tegra210/Makefile.inc
View file

@ -12,7 +12,6 @@ bootblock-y += monotonic_timer.c
bootblock-y += padconfig.c
bootblock-y += power.c
bootblock-y += funitcfg.c
bootblock-y += reset.c
bootblock-y += ../tegra/gpio.c
bootblock-y += ../tegra/i2c.c
bootblock-y += ../tegra/pingroup.c
@ -41,7 +40,6 @@ romstage-y += cbmem.c
romstage-y += ccplex.c
romstage-y += clock.c
romstage-y += cpu.c
romstage-y += reset.c
romstage-y += spi.c
romstage-y += i2c.c
romstage-y += dma.c
@ -87,7 +85,6 @@ ramstage-y += gic.c
ramstage-y += monotonic_timer.c
ramstage-y += padconfig.c
ramstage-y += funitcfg.c
ramstage-y += reset.c
ramstage-y += ram_code.c
ramstage-y += ../tegra/apbmisc.c
ramstage-y += ../tegra/gpio.c

25
src/soc/nvidia/tegra210/reset.c
View file

@ -1,25 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <reset.h>
/*
* Promote cpu_reset() to a hard_reset(). A shallower reset can be added,
* if needed, at a later time.
*/
void cpu_reset(void)
{
hard_reset();
}