mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
e6711e269a
The Tegra210 SoC never had a proper cpu_reset() implementation, so it's
pointless to pretend there is one. Most ARM SoCs/boards only define
hard_reset() at the moment anyway, so let's stick with that.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ifeb6b0b2a4417bdb13908ceb0aa4e382b40a91c5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c25b2a18fa
Original-Change-Id: I40f39921fa99d6dfabf818e7abe7a5732341cf4f
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19786
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/521025
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
89 lines
2.3 KiB
C
89 lines
2.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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* Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <boardid.h>
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#include <console/console.h>
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#include <delay.h>
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#include <device/i2c.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include "pmic.h"
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#include "reset.h"
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enum {
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MAX77620_I2C_ADDR = 0x3c
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};
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struct max77620_init_reg {
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u8 reg;
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u8 val;
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u8 delay;
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};
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static struct max77620_init_reg init_list[] = {
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/* TODO */
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};
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static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int delay)
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{
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if (i2c_writeb(bus, MAX77620_I2C_ADDR, reg, val)) {
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printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n",
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__func__, reg, val);
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/* Reset the board on any PMIC write error */
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hard_reset();
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} else {
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if (delay)
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udelay(500);
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}
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}
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static void pmic_slam_defaults(unsigned bus)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(init_list); i++) {
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struct max77620_init_reg *reg = &init_list[i];
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pmic_write_reg(bus, reg->reg, reg->val, reg->delay);
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}
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}
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void pmic_init(unsigned bus)
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{
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/* Restore PMIC POR defaults, in case kernel changed 'em */
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pmic_slam_defaults(bus);
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/* Setup/Enable GPIO5 - VDD_CPU_REG_EN */
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pmic_write_reg(bus, MAX77620_GPIO5_REG, 0x09, 1);
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/* Setup/Enable GPIO1 - VDD_HDMI_5V0_BST_EN -- ??? */
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pmic_write_reg(bus, MAX77620_GPIO1_REG, 0x09, 1);
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/* GPIO 0,1,5,6,7 = GPIO, 2,3,4 = alt mode */
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pmic_write_reg(bus, MAX77620_AME_GPIO, 0x1c, 1);
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/* Disable SD1 Remote Sense, Set SD1 for LPDDR4 to 1.125v? */
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pmic_write_reg(bus, MAX77620_CNFG2SD_REG, 0x04, 1);
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pmic_write_reg(bus, MAX77620_SD1_REG, 0x2a, 1);
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/* CNFG1_L2 = 0xF2 for 3.3v, enabled */
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pmic_write_reg(bus, MAX77620_CNFG1_L2_REG, 0xf2, 1);
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/* CNFG1_L1 = 0xCA for 1.05v, enabled */
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pmic_write_reg(bus, MAX77620_CNFG1_L1_REG, 0xca, 1);
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printk(BIOS_DEBUG, "PMIC init done\n");
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}
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