From e5772aebf82947c8596d4c2f195e67599a371108 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Sat, 21 Jan 2017 16:55:03 -0800 Subject: [PATCH] UPSTREAM: soc/intel/skylake: Include I2C code in romstage The lpss_i2c driver is enabled in romstage, so the SOC needs to export the pre-ram compatible I2C controller info, which for skylake is in the bootblock/i2c.c file. This was not causing a compiler error in normal use, but when adding I2C debug code in romstage it failed to compile. With this added, I can now do I2C transactions in romstage. BUG=none BRANCH=none TEST=none Change-Id: Ieb17a32000c65a5f1577d3897ddaa869ef63ee32 Signed-off-by: Duncan Laurie Original-Commit-Id: 4234ca276419314a0df598c7375c683def67ab1a Original-Change-Id: I0778b0497d0b6936df47c29b2ce942c8d90cf39b Original-Signed-off-by: Duncan Laurie Original-Reviewed-on: https://review.coreboot.org/18198 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/431208 Commit-Ready: Duncan Laurie Tested-by: Duncan Laurie Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 3a474e725e..4b6fcfc1f1 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -38,6 +38,7 @@ verstage-y += spi.c romstage-y += flash_controller.c romstage-y += gpio.c +romstage-y += bootblock/i2c.c romstage-y += memmap.c romstage-y += monotonic_timer.c romstage-y += me.c