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new mobo!

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ron
This commit is contained in:
Ronald G. Minnich 2004-02-05 15:35:40 +00:00
parent 803eeae5d2
commit e22ced4257
3 changed files with 66 additions and 0 deletions
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28
src/mainboard/chaintech/7kjd/Config Executable file
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arch i386
mainboardinit cpu/i386/entry16.inc
mainboardinit cpu/i386/entry32.inc
ldscript cpu/i386/entry16.lds
ldscript cpu/i386/entry32.lds
mainboardinit superio/via/vt8231/setup_serial.inc
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
mainboardinit cpu/k7/earlymtrr.inc
mainboardinit southbridge/via/vt8231/ideconfig.inc
northbridge amd/amd76x
southbridge via/vt8231
keyboard pc80
cpu k7
object mainboard.o
object irq_tables.o
option HAVE_PIRQ_TABLE=1
option ENABLE_FIXED_AND_VARIABLE_MTRRS=1
option SUPERIO_DEVFN=0X88
option ENABLE_IDE_NATIVE_MODE=0
#option FINAL_MAINBOARD_FIXUP=1

32
src/mainboard/chaintech/7kjd/irq_tables.c Executable file
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/* This file was generated by getpir.c, do not modify!
(but if you do, please run checkpir on it to verify)
Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
*/
#include <arch/pirq_routing.h>
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32+16*8, /* there can be total 8 devices on the bus */
0, /* Where the interrupt router lies (bus) */
0, /* Where the interrupt router lies (dev) */
0xc20, /* IRQs devoted exclusively to PCI usage */
0, /* Vendor */
0, /* Device */
0, /* Crap (miniport) */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0x9d, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
{
{0,0x50, {{0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}}, 0x2, 0},
{0,0x58, {{0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}}, 0x3, 0},
{0,0x60, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x4, 0},
{0,0x68, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x5, 0},
{0,0x70, {{0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}}, 0x6, 0},
{0x1,0x28, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x7, 0},
{0,0x8, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0, 0},
{0x80,0, {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
}
};

6
src/mainboard/chaintech/7kjd/mainboard.c Executable file
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void
mainboard_fixup()
{
void southbridge_fixup(void);
southbridge_fixup();
}