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https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
Support files for l440gx
This commit is contained in:
Ronald G. Minnich
parent
f4b8d48483
commit
e14a836658
3 changed files with 329 additions and 0 deletions
94
src/mainboard/intel/l440gx/Makefile
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94
src/mainboard/intel/l440gx/Makefile
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CPUFLAGS=-DL440GX -Di686 -Di586 -DINTEL_BRIDGE_CONFIG -DPIIX4E_NVRAM
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CPUFLAGS += -D__KERNEL__
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CPUFLAGS += -DINTEL_PPRO_MTRR -DPIIX4E_KEYBOARD
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CPUFLAGS += -DSMP
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#CPUFLAGS += -DHAVE_FRAMEBUFFER
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CPUFLAGS += -DNEWPCI
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CPUFLAGS += -DZKERNEL_START=0xfff40000
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CPUFLAGS += -DZKERNEL_MASK=0x3ed
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CPUFLAGS += -DSERIAL_CONSOLE
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CPUFLAGS += -DCMD_LINE='"ro root=/dev/hda1 console=ttyS0,115200 debug 3 single"'
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CPUFLAGS += -DPIIX4_DEVFN=0x90
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#CPUFLAGS += -DUPDATE_MICROCODE
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phlash_floppy: phlash
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mcopy -o /tmp/$(PHLASH_BASE_NAME).bi? a:
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crt0.s: crt0.S ../../chip/intel/intel_start32.S ../../chip/intel/intel_440ram-2.S
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include ../Makefile.common
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# here begins stupid stuff for the phlash program. It's ugly.
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#PHLASH_BASE_NAME=p11-0105
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PHLASH_BASE_NAME=p11-0102
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#PHLASH_BASE_NAME=p12-0115
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#PHLASH_BASE_NAME=p13-0125
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phlash: vmlinux.bin.gz linuxbios.rom headers
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rm -f xa?
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split -b 64k vmlinux.bin.gz
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# Now just touch them if we have a really
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# small kernel!
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touch xaa xab xac xad xae xaf xag xah
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# this if starting at bank 4, and proceeding on. Unused banks are dups
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# intel nvram is odd all of the banks are byte swapped
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cat $(PHLASH_BASE_NAME).bi1.header xaa > $(PHLASH_BASE_NAME).bi1
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cat $(PHLASH_BASE_NAME).bi3.header xab > $(PHLASH_BASE_NAME).bi3
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cat $(PHLASH_BASE_NAME).bi2.header xac > $(PHLASH_BASE_NAME).bi2
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cat $(PHLASH_BASE_NAME).bi4.header xad > $(PHLASH_BASE_NAME).bi4
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cat $(PHLASH_BASE_NAME).bi7.header xae > $(PHLASH_BASE_NAME).bi7
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cat $(PHLASH_BASE_NAME).bi6.header xaf > $(PHLASH_BASE_NAME).bi6
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cat $(PHLASH_BASE_NAME).bi9.header xag > $(PHLASH_BASE_NAME).bi9
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cat $(PHLASH_BASE_NAME).bi8.header xah > $(PHLASH_BASE_NAME).bi8
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cat $(PHLASH_BASE_NAME).bia.header linuxbios.rom > $(PHLASH_BASE_NAME).bia
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# Part o & 5 seem not to be written reliably for some reason...
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cat $(PHLASH_BASE_NAME).bio.header /dev/null > $(PHLASH_BASE_NAME).bio
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cat $(PHLASH_BASE_NAME).bi5.header /dev/null > $(PHLASH_BASE_NAME).bi5
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sh -x BUILD_PHLASH_FILES $(PHLASH_BASE_NAME)
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headers: \
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$(PHLASH_BASE_NAME).bi1.header \
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$(PHLASH_BASE_NAME).bi2.header \
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$(PHLASH_BASE_NAME).bi3.header \
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$(PHLASH_BASE_NAME).bi4.header \
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$(PHLASH_BASE_NAME).bi5.header \
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$(PHLASH_BASE_NAME).bi6.header \
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$(PHLASH_BASE_NAME).bi7.header \
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$(PHLASH_BASE_NAME).bi8.header \
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$(PHLASH_BASE_NAME).bi9.header \
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$(PHLASH_BASE_NAME).bia.header \
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$(PHLASH_BASE_NAME).bio.header
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# This builds the headers from the intel flash disk.
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# we are not distributing this disk; you need to get it.
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BUILDHEADER=dd if=$< of=$@ bs=1 count=160
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$(PHLASH_BASE_NAME).bi1.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi1
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bi2.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi2
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bi3.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi3
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bi4.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi4
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bi5.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi5
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bi6.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi6
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bi7.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi7
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bi8.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi8
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bi9.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi9
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bia.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bia
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bio.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bio
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$(BUILDHEADER)
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clean::
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rm -f $(PHLASH_BASE_NAME)*
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119
src/mainboard/intel/l440gx/crt0.S
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119
src/mainboard/intel/l440gx/crt0.S
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@ -0,0 +1,119 @@
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/*
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* $ $
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*
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*/
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#include <rom/asm.h>
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#include <rom/intel.h>
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#include "intel_conf.h"
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/*
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* This is the entry code (the mkrom(8) utility makes a jumpvector
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* to this adddess.
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*
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* When we get here we are in x86 real mode.
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*
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* %cs = 0xf000 %ip = 0x0000
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* %ds = 0x0000 %es = 0x0000
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* %dx = 0x0yxx (y = 3 for i386, 5 for pentium, 6 for P6,
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* where x is undefined)
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* %fl = 0x0002
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*/
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.text
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.code16
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#include "intel_start32.S"
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#include "NSC_SuperIO.S"
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#include "serial.S"
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TTYS0_TX_STRING($ttyS0_test)
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/* initialize the RAM */
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/* different for each motherboard */
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#include "intel_440ram-2.S"
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#include "intel_ram.S"
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#undef RAMTEST
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#include "ramtest.S"
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#if 0
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movl $0x00000000, %eax
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movl $0x0009ffff, %ebx
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movl $24,%ecx
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CALLSP(ramtest)
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#endif
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#if 0
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movl $0x08000000, %eax
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movl $0x08001000, %ebx
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movl $24,%ecx
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CALLSP(ramtest)
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movl $0x10000000, %eax
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movl $0x10001000, %ebx
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movl $24,%ecx
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CALLSP(ramtest)
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#endif
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/*
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* Copy data into RAM and clear the BSS. Since these segments
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* isn't really that big we just copy/clear using bytes, not
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* double words.
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*/
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intel_chip_post_macro(0x11) /* post 11 */
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TTYS0_TX_STRING($str_after_ram)
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cld /* clear direction flag */
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leal EXT(_ldata), %esi
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leal EXT(_data), %edi
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movl $EXT(_eldata), %ecx
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subl %esi, %ecx
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jz .Lnodata /* should not happen */
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rep
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movsb
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.Lnodata:
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intel_chip_post_macro(0x12) /* post 12 */
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TTYS0_TX_STRING($str_after_copy)
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/** clear stack */
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xorl %edi, %edi
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movl $_PDATABASE, %ecx
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xorl %eax, %eax
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rep
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stosb
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/** clear bss */
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leal EXT(_bss), %edi
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movl $EXT(_ebss), %ecx
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subl %edi, %ecx
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jz .Lnobss
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xorl %eax, %eax
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rep
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stosb
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.Lnobss:
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/*
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* Now we are finished. Memory is up, data is copied and
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* bss is cleared. Now we call the ``main´´ routine and
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* let it do the rest.
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*/
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intel_chip_post_macro(0xfe) /* post fe */
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TTYS0_TX_STRING($str_pre_main)
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/* set new stack */
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movl $_PDATABASE, %esp
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/* memory is up. Let's do the rest in C -- much easier. */
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call EXT(intel_main)
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/*NOTREACHED*/
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.Lhlt: hlt
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jmp .Lhlt
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ttyS0_test: .string "\r\n\r\nHello world!!\r\n"
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str_after_ram: .string "Ram Initialize?\r\n"
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str_after_copy: .string "after copy?\r\n"
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str_pre_main: .string "before main\r\n"
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newline: .string "\r\n"
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116
src/mainboard/intel/l440gx/ldscript.ld
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116
src/mainboard/intel/l440gx/ldscript.ld
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/*
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* Bootstrap code for the STPC Consumer
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* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
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*
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* $Id$
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*
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*/
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/* oh, barf. This won't work if all you use is .o's. -- RGM */
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/*
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* Written by Johan Rydberg, based on work by Daniel Kahlin.
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*/
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/*
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* We use ELF as output format. So that we can
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* debug the code in some form.
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*/
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OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
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OUTPUT_ARCH(i386)
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/*
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* Memory map:
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*
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* 0x00000 (4*4096 bytes) : stack
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* 0x04000 (4096 bytes) : private data
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* 0x05000 : data space
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* 0x90000 : kernel stack
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* 0xf0000 (64 Kbyte) : EPROM
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*/
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MEMORY
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{
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ram (rwx) : ORIGIN = 0x00000000, LENGTH = 128M /* 128 MB memory is
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* max for STPC */
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rom (rx) : ORIGIN = 0x000f0000, LENGTH = 128K /* 128 K EPROM */
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}
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_PDATABASE = 0x04000;
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_RAMBASE = 0x05000;
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_KERNSTK = 0x90000;
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/* should be parameterized but is not, yuck! */
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/*
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_ROMBASE = 0xe0000;
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*/
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_ROMBASE = 0xf0000;
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/*
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* Entry point is not really nececary, since the mkrom(8)
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* tool creates a entry point that jumps to $0xc000:0x0000.
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*/
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/* baloney, but ... RGM*/
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ENTRY(_start)
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SECTIONS {
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/*
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* First we place the code and read only data (typically const declared).
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* This get placed in rom.
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*/
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.text _ROMBASE : {
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_text = .;
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*(.text);
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*(.rodata);
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_etext = .;
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}
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_pdata = .;
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/*
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.pdata _PDATABASE : AT ( LOADADDR(.text) + SIZEOF(.text) +
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SIZEOF(.rodata)) {
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*/
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.pdata _PDATABASE : AT ( _etext ) {
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*(.pdata);
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}
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_epdata = LOADADDR(.pdata) + SIZEOF(.pdata);
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/*
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* After the code we place initialized data (typically initialized
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* global variables). This gets copied into ram by startup code.
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* __data_start and __data_end shows where in ram this should be placed,
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* whereas __data_loadstart and __data_loadend shows where in rom to
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* copy from.
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*/
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.data _RAMBASE : AT ( LOADADDR(.pdata) + SIZEOF(.pdata) ) {
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_data = .;
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*(.data)
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*(.sdata)
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*(.sdata2)
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*(.got)
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_edata = .;
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}
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_ldata = LOADADDR(.data);
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_eldata = LOADADDR(.data) + SIZEOF(.data);
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/*
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* bss does not contain data, it is just a space that should be zero
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* initialized on startup. (typically uninitialized global variables)
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* crt0.S fills between __bss_start and __bss_end with zeroes.
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*/
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.bss ( ADDR(.data) + SIZEOF(.data) ) : {
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_bss = .;
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*(.bss)
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*(.sbss)
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*(COMMON)
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_ebss = .;
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_heap = .;
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}
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}
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/*
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* This provides the start and end address for the whole image
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*/
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_image = LOADADDR(.text);
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_eimage = LOADADDR(.data) + SIZEOF(.data);
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/* EOF */
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