From e14a8366581a580f4e801e4000858eeef1db97c5 Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Thu, 19 Oct 2000 02:27:25 +0000 Subject: [PATCH] Support files for l440gx --- src/mainboard/intel/l440gx/Makefile | 94 +++++++++++++++++++ src/mainboard/intel/l440gx/crt0.S | 119 +++++++++++++++++++++++++ src/mainboard/intel/l440gx/ldscript.ld | 116 ++++++++++++++++++++++++ 3 files changed, 329 insertions(+) create mode 100644 src/mainboard/intel/l440gx/Makefile create mode 100644 src/mainboard/intel/l440gx/crt0.S create mode 100644 src/mainboard/intel/l440gx/ldscript.ld diff --git a/src/mainboard/intel/l440gx/Makefile b/src/mainboard/intel/l440gx/Makefile new file mode 100644 index 0000000000..6803292094 --- /dev/null +++ b/src/mainboard/intel/l440gx/Makefile @@ -0,0 +1,94 @@ +CPUFLAGS=-DL440GX -Di686 -Di586 -DINTEL_BRIDGE_CONFIG -DPIIX4E_NVRAM +CPUFLAGS += -D__KERNEL__ +CPUFLAGS += -DINTEL_PPRO_MTRR -DPIIX4E_KEYBOARD +CPUFLAGS += -DSMP +#CPUFLAGS += -DHAVE_FRAMEBUFFER +CPUFLAGS += -DNEWPCI +CPUFLAGS += -DZKERNEL_START=0xfff40000 +CPUFLAGS += -DZKERNEL_MASK=0x3ed +CPUFLAGS += -DSERIAL_CONSOLE +CPUFLAGS += -DCMD_LINE='"ro root=/dev/hda1 console=ttyS0,115200 debug 3 single"' +CPUFLAGS += -DPIIX4_DEVFN=0x90 +#CPUFLAGS += -DUPDATE_MICROCODE + +phlash_floppy: phlash + mcopy -o /tmp/$(PHLASH_BASE_NAME).bi? a: + +crt0.s: crt0.S ../../chip/intel/intel_start32.S ../../chip/intel/intel_440ram-2.S + +include ../Makefile.common + +# here begins stupid stuff for the phlash program. It's ugly. + +#PHLASH_BASE_NAME=p11-0105 +PHLASH_BASE_NAME=p11-0102 +#PHLASH_BASE_NAME=p12-0115 +#PHLASH_BASE_NAME=p13-0125 + +phlash: vmlinux.bin.gz linuxbios.rom headers + rm -f xa? + split -b 64k vmlinux.bin.gz +# Now just touch them if we have a really +# small kernel! + touch xaa xab xac xad xae xaf xag xah +# this if starting at bank 4, and proceeding on. Unused banks are dups +# intel nvram is odd all of the banks are byte swapped + cat $(PHLASH_BASE_NAME).bi1.header xaa > $(PHLASH_BASE_NAME).bi1 + cat $(PHLASH_BASE_NAME).bi3.header xab > $(PHLASH_BASE_NAME).bi3 + cat $(PHLASH_BASE_NAME).bi2.header xac > $(PHLASH_BASE_NAME).bi2 + cat $(PHLASH_BASE_NAME).bi4.header xad > $(PHLASH_BASE_NAME).bi4 + cat $(PHLASH_BASE_NAME).bi7.header xae > $(PHLASH_BASE_NAME).bi7 + cat $(PHLASH_BASE_NAME).bi6.header xaf > $(PHLASH_BASE_NAME).bi6 + cat $(PHLASH_BASE_NAME).bi9.header xag > $(PHLASH_BASE_NAME).bi9 + cat $(PHLASH_BASE_NAME).bi8.header xah > $(PHLASH_BASE_NAME).bi8 + cat $(PHLASH_BASE_NAME).bia.header linuxbios.rom > $(PHLASH_BASE_NAME).bia + # Part o & 5 seem not to be written reliably for some reason... + cat $(PHLASH_BASE_NAME).bio.header /dev/null > $(PHLASH_BASE_NAME).bio + cat $(PHLASH_BASE_NAME).bi5.header /dev/null > $(PHLASH_BASE_NAME).bi5 + sh -x BUILD_PHLASH_FILES $(PHLASH_BASE_NAME) + +headers: \ + $(PHLASH_BASE_NAME).bi1.header \ + $(PHLASH_BASE_NAME).bi2.header \ + $(PHLASH_BASE_NAME).bi3.header \ + $(PHLASH_BASE_NAME).bi4.header \ + $(PHLASH_BASE_NAME).bi5.header \ + $(PHLASH_BASE_NAME).bi6.header \ + $(PHLASH_BASE_NAME).bi7.header \ + $(PHLASH_BASE_NAME).bi8.header \ + $(PHLASH_BASE_NAME).bi9.header \ + $(PHLASH_BASE_NAME).bia.header \ + $(PHLASH_BASE_NAME).bio.header + +# This builds the headers from the intel flash disk. +# we are not distributing this disk; you need to get it. +BUILDHEADER=dd if=$< of=$@ bs=1 count=160 + +$(PHLASH_BASE_NAME).bi1.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi1 + $(BUILDHEADER) +$(PHLASH_BASE_NAME).bi2.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi2 + $(BUILDHEADER) +$(PHLASH_BASE_NAME).bi3.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi3 + $(BUILDHEADER) +$(PHLASH_BASE_NAME).bi4.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi4 + $(BUILDHEADER) +$(PHLASH_BASE_NAME).bi5.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi5 + $(BUILDHEADER) +$(PHLASH_BASE_NAME).bi6.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi6 + $(BUILDHEADER) +$(PHLASH_BASE_NAME).bi7.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi7 + $(BUILDHEADER) +$(PHLASH_BASE_NAME).bi8.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi8 + $(BUILDHEADER) +$(PHLASH_BASE_NAME).bi9.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi9 + $(BUILDHEADER) +$(PHLASH_BASE_NAME).bia.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bia + $(BUILDHEADER) +$(PHLASH_BASE_NAME).bio.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bio + $(BUILDHEADER) + + + +clean:: + rm -f $(PHLASH_BASE_NAME)* + diff --git a/src/mainboard/intel/l440gx/crt0.S b/src/mainboard/intel/l440gx/crt0.S new file mode 100644 index 0000000000..4f80dd3a14 --- /dev/null +++ b/src/mainboard/intel/l440gx/crt0.S @@ -0,0 +1,119 @@ +/* + * $ $ + * + */ + +#include +#include + +#include "intel_conf.h" + +/* + * This is the entry code (the mkrom(8) utility makes a jumpvector + * to this adddess. + * + * When we get here we are in x86 real mode. + * + * %cs = 0xf000 %ip = 0x0000 + * %ds = 0x0000 %es = 0x0000 + * %dx = 0x0yxx (y = 3 for i386, 5 for pentium, 6 for P6, + * where x is undefined) + * %fl = 0x0002 + */ + .text + .code16 + +#include "intel_start32.S" + +#include "NSC_SuperIO.S" + +#include "serial.S" + + TTYS0_TX_STRING($ttyS0_test) + + /* initialize the RAM */ + /* different for each motherboard */ + +#include "intel_440ram-2.S" +#include "intel_ram.S" +#undef RAMTEST +#include "ramtest.S" + +#if 0 + movl $0x00000000, %eax + movl $0x0009ffff, %ebx + movl $24,%ecx + CALLSP(ramtest) +#endif + +#if 0 + movl $0x08000000, %eax + movl $0x08001000, %ebx + movl $24,%ecx + CALLSP(ramtest) + + movl $0x10000000, %eax + movl $0x10001000, %ebx + movl $24,%ecx + CALLSP(ramtest) +#endif + +/* + * Copy data into RAM and clear the BSS. Since these segments + * isn't really that big we just copy/clear using bytes, not + * double words. + */ + intel_chip_post_macro(0x11) /* post 11 */ + TTYS0_TX_STRING($str_after_ram) + + cld /* clear direction flag */ + leal EXT(_ldata), %esi + leal EXT(_data), %edi + movl $EXT(_eldata), %ecx + subl %esi, %ecx + jz .Lnodata /* should not happen */ + rep + movsb +.Lnodata: + intel_chip_post_macro(0x12) /* post 12 */ + TTYS0_TX_STRING($str_after_copy) + + /** clear stack */ + xorl %edi, %edi + movl $_PDATABASE, %ecx + xorl %eax, %eax + rep + stosb + /** clear bss */ + leal EXT(_bss), %edi + movl $EXT(_ebss), %ecx + subl %edi, %ecx + jz .Lnobss + xorl %eax, %eax + rep + stosb +.Lnobss: + +/* + * Now we are finished. Memory is up, data is copied and + * bss is cleared. Now we call the ``main´´ routine and + * let it do the rest. + */ + intel_chip_post_macro(0xfe) /* post fe */ + TTYS0_TX_STRING($str_pre_main) + + /* set new stack */ + movl $_PDATABASE, %esp + + +/* memory is up. Let's do the rest in C -- much easier. */ + call EXT(intel_main) + /*NOTREACHED*/ +.Lhlt: hlt + jmp .Lhlt + +ttyS0_test: .string "\r\n\r\nHello world!!\r\n" +str_after_ram: .string "Ram Initialize?\r\n" +str_after_copy: .string "after copy?\r\n" +str_pre_main: .string "before main\r\n" +newline: .string "\r\n" diff --git a/src/mainboard/intel/l440gx/ldscript.ld b/src/mainboard/intel/l440gx/ldscript.ld new file mode 100644 index 0000000000..c1669e1d79 --- /dev/null +++ b/src/mainboard/intel/l440gx/ldscript.ld @@ -0,0 +1,116 @@ +/* + * Bootstrap code for the STPC Consumer + * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. + * + * $Id$ + * + */ +/* oh, barf. This won't work if all you use is .o's. -- RGM */ + +/* + * Written by Johan Rydberg, based on work by Daniel Kahlin. + */ +/* + * We use ELF as output format. So that we can + * debug the code in some form. + */ +OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") +OUTPUT_ARCH(i386) + +/* + * Memory map: + * + * 0x00000 (4*4096 bytes) : stack + * 0x04000 (4096 bytes) : private data + * 0x05000 : data space + * 0x90000 : kernel stack + * 0xf0000 (64 Kbyte) : EPROM + */ +MEMORY +{ + ram (rwx) : ORIGIN = 0x00000000, LENGTH = 128M /* 128 MB memory is + * max for STPC */ + rom (rx) : ORIGIN = 0x000f0000, LENGTH = 128K /* 128 K EPROM */ +} + +_PDATABASE = 0x04000; +_RAMBASE = 0x05000; +_KERNSTK = 0x90000; +/* should be parameterized but is not, yuck! */ +/* +_ROMBASE = 0xe0000; + */ +_ROMBASE = 0xf0000; + +/* + * Entry point is not really nececary, since the mkrom(8) + * tool creates a entry point that jumps to $0xc000:0x0000. + */ +/* baloney, but ... RGM*/ +ENTRY(_start) + +SECTIONS { + /* + * First we place the code and read only data (typically const declared). + * This get placed in rom. + */ + .text _ROMBASE : { + _text = .; + *(.text); + *(.rodata); + _etext = .; + } + + _pdata = .; + +/* + .pdata _PDATABASE : AT ( LOADADDR(.text) + SIZEOF(.text) + + SIZEOF(.rodata)) { + */ + .pdata _PDATABASE : AT ( _etext ) { + *(.pdata); + } + + _epdata = LOADADDR(.pdata) + SIZEOF(.pdata); + + /* + * After the code we place initialized data (typically initialized + * global variables). This gets copied into ram by startup code. + * __data_start and __data_end shows where in ram this should be placed, + * whereas __data_loadstart and __data_loadend shows where in rom to + * copy from. + */ + .data _RAMBASE : AT ( LOADADDR(.pdata) + SIZEOF(.pdata) ) { + _data = .; + *(.data) + *(.sdata) + *(.sdata2) + *(.got) + _edata = .; + } + + _ldata = LOADADDR(.data); + _eldata = LOADADDR(.data) + SIZEOF(.data); + + /* + * bss does not contain data, it is just a space that should be zero + * initialized on startup. (typically uninitialized global variables) + * crt0.S fills between __bss_start and __bss_end with zeroes. + */ + .bss ( ADDR(.data) + SIZEOF(.data) ) : { + _bss = .; + *(.bss) + *(.sbss) + *(COMMON) + _ebss = .; + _heap = .; + } +} + +/* + * This provides the start and end address for the whole image + */ +_image = LOADADDR(.text); +_eimage = LOADADDR(.data) + SIZEOF(.data); + +/* EOF */