mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
update status for smartcore-p3
comment out PIIX4E code in the l440gx mainboard init set up PIIX4E PM and SMBUS at < 0x1000 addresses
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parent
a3ba9bf178
commit
dda0296a29
3 changed files with 41 additions and 12 deletions
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@ -7,19 +7,19 @@
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owner: Ron Minnich
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email: rminnich@lanl.gov
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#status: One of unsupported, unstable, stable
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status: unstable
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explanation:
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flash-types:
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payload-types:
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status: stable
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explanation: Now works as of current CVS
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flash-types: 256K or 512K PLCC (e.g. sst28SF040)
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payload-types: etherboot
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# e.g. linux, plan 9, wince, etc.
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OS-types:
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OS-types: Linux
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# e.g. "Plan 9 interrupts don't work on this chipset"
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OS-issues:
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console-types:
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OS-issues: None
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console-types:Serial
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# vga is unsupported, unstable, or stable
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vga:
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vga:unsupported
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# Last-known-good follows the internationl date standard: day/month/year
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last-known-good: 0/0/0000
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last-known-good: 15/11/2002
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Comments:
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Links:
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Mainboard-revision:
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@ -54,7 +54,7 @@ void mainboard_fixup()
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printk_debug("Disable Nmi\n");
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outb(0, 0x70);
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#if 0 // moved to piix4e southbridge code
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printk_debug("enabling smbus\n");
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#if 0
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smbus_io = NewPciIo(0x10);
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@ -74,7 +74,7 @@ void mainboard_fixup()
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#endif
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pci_write_config_dword(pm_pcidev, 0x40, pm_io | 1); /* iobase addr */
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pci_write_config_byte(pm_pcidev, 0x80, 1); /* enable pm io address */
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#endif
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printk_debug("disabling smi\n");
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/* GLBEN */
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outw(0x00, pm_io + 0x20);
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@ -6,6 +6,9 @@
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void
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southbridge_fixup()
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{
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struct pci_dev *pm_pcidev;
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unsigned smbus_io, pm_io;
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#if (CONFIG_LINUXBIOS_ENABLE_IDE == 1)
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struct pci_dev *pcidev;
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struct pci_dev *pcidevdebug;
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@ -38,9 +41,35 @@ southbridge_fixup()
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printk_info("Word at 4 is now 0x%04x\n", c);
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#endif
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}
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#endif
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pm_pcidev = pci_find_device(0x8086, 0x7113, 0);
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if (! pm_pcidev) {
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printk_err("Can't find piix4e PM\n");
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} else {
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printk_debug("enabling smbus\n");
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#if 0
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smbus_io = NewPciIo(0x10);
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#else
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smbus_io = 0xFFF0;
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#endif
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pci_write_config_dword(pm_pcidev, 0x90, smbus_io | 1); /* iobase addr */
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pci_write_config_byte(pm_pcidev, 0xd2, (0x4 << 1) | 1); /* smbus enable */
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pci_write_config_word(pm_pcidev, 0x4, 1); /* iospace enable */
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printk_debug("enable pm functions\n");
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#if 0
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pm_io = NewPciIo(0x40);
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#else
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pm_io = 0xFF80;
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#endif
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pci_write_config_dword(pm_pcidev, 0x40, pm_io | 1); /* iobase addr */
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pci_write_config_byte(pm_pcidev, 0x80, 1); /* enable pm io address */
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}
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printk_info("done.\n");
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#endif
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}
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void nvram_on()
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