From dda0296a298dac6b2b3ac63f049e9a8e4c44176e Mon Sep 17 00:00:00 2001
From: "Ronald G. Minnich" <rminnich@gmail.com>
Date: Fri, 15 Nov 2002 21:26:45 +0000
Subject: [PATCH] update status for smartcore-p3 comment out PIIX4E code in the
 l440gx mainboard init set up PIIX4E PM and SMBUS at < 0x1000 addresses

---
 .../digitallogic/smartcore-p3/STATUS          | 18 +++++------
 src/mainboard/intel/l440gx/mainboard.c        |  4 +--
 src/southbridge/intel/piix4e/southbridge.c    | 31 ++++++++++++++++++-
 3 files changed, 41 insertions(+), 12 deletions(-)

diff --git a/src/mainboard/digitallogic/smartcore-p3/STATUS b/src/mainboard/digitallogic/smartcore-p3/STATUS
index 72e4518f71..b99624cef3 100644
--- a/src/mainboard/digitallogic/smartcore-p3/STATUS
+++ b/src/mainboard/digitallogic/smartcore-p3/STATUS
@@ -7,19 +7,19 @@
 owner:	Ron Minnich
 email:	rminnich@lanl.gov
 #status: One of unsupported, unstable, stable
-status: unstable
-explanation: 
-flash-types: 
-payload-types: 
+status: stable
+explanation: Now works as of current CVS
+flash-types: 256K or 512K PLCC (e.g. sst28SF040)
+payload-types: etherboot
 # e.g. linux, plan 9, wince, etc.
-OS-types: 
+OS-types: Linux
 # e.g. "Plan 9 interrupts don't work on this chipset"
-OS-issues:
-console-types:
+OS-issues: None
+console-types:Serial
 # vga is unsupported, unstable, or stable
-vga:
+vga:unsupported
 # Last-known-good follows the internationl date standard: day/month/year
-last-known-good: 0/0/0000
+last-known-good: 15/11/2002
 Comments: 
 Links:
 Mainboard-revision: 
diff --git a/src/mainboard/intel/l440gx/mainboard.c b/src/mainboard/intel/l440gx/mainboard.c
index 58071de5ed..d68d1a5149 100644
--- a/src/mainboard/intel/l440gx/mainboard.c
+++ b/src/mainboard/intel/l440gx/mainboard.c
@@ -54,7 +54,7 @@ void mainboard_fixup()
 
 	printk_debug("Disable Nmi\n");
 	outb(0, 0x70);
-
+#if 0 // moved to piix4e southbridge code
 	printk_debug("enabling smbus\n");
 #if 0
 	smbus_io = NewPciIo(0x10);
@@ -74,7 +74,7 @@ void mainboard_fixup()
 #endif
 	pci_write_config_dword(pm_pcidev, 0x40, pm_io | 1); /* iobase addr */
 	pci_write_config_byte(pm_pcidev, 0x80, 1);  /* enable pm io address */
-
+#endif
 	printk_debug("disabling smi\n");
 	/* GLBEN */
 	outw(0x00,      pm_io + 0x20);
diff --git a/src/southbridge/intel/piix4e/southbridge.c b/src/southbridge/intel/piix4e/southbridge.c
index 9a6253a5a6..208fb6f651 100644
--- a/src/southbridge/intel/piix4e/southbridge.c
+++ b/src/southbridge/intel/piix4e/southbridge.c
@@ -6,6 +6,9 @@
 void
 southbridge_fixup()
 {
+
+	struct pci_dev *pm_pcidev;
+	unsigned smbus_io, pm_io;
 #if (CONFIG_LINUXBIOS_ENABLE_IDE == 1)
         struct pci_dev *pcidev;
         struct pci_dev *pcidevdebug;
@@ -38,9 +41,35 @@ southbridge_fixup()
 		printk_info("Word at 4 is now 0x%04x\n", c);
 #endif
 	}
+#endif
+	pm_pcidev = pci_find_device(0x8086, 0x7113, 0);
+	if (! pm_pcidev) {
+		printk_err("Can't find piix4e PM\n");
+	} else {
+	  
+	  printk_debug("enabling smbus\n");
+#if 0
+	  smbus_io = NewPciIo(0x10);
+#else
+	  smbus_io = 0xFFF0;
+#endif
+	  pci_write_config_dword(pm_pcidev, 0x90, smbus_io | 1); /* iobase addr */
+	  pci_write_config_byte(pm_pcidev, 0xd2,  (0x4 << 1) | 1); /* smbus enable */
+	  pci_write_config_word(pm_pcidev, 0x4, 1); /* iospace enable */
+	  
+	  
+	  printk_debug("enable pm functions\n");
+#if 0
+	  pm_io = NewPciIo(0x40);
+#else
+	  pm_io = 0xFF80;
+#endif
+	  pci_write_config_dword(pm_pcidev, 0x40, pm_io | 1); /* iobase addr */
+	  pci_write_config_byte(pm_pcidev, 0x80, 1);  /* enable pm io address */
+	}
 
         printk_info("done.\n");
-#endif
+
 }
 
 void nvram_on()