mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
Some attempts at making acer autosizing work. All failed.
This commit is contained in:
Ronald G. Minnich
parent
d6fa756090
commit
b93da0a299
4 changed files with 3438 additions and 0 deletions
174
romimages/RON_ASUS_CUA_DOC2/Makefile
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174
romimages/RON_ASUS_CUA_DOC2/Makefile
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@ -0,0 +1,174 @@
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CPUFLAGS=-Di386 -Di486 -Di686 -Di586
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# Well, we have old silicon
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CPUFLAGS += -DINTEL_BRIDGE_CONFIG
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CPUFLAGS += -DINTEL_PPRO_MTRR
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CPUFLAGS += -DNEWPCI
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CPUFLAGS += -DSERIAL_CONSOLE
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CPUFLAGS += -DFINAL_MAINBOARD_FIXUP
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CPUFLAGS += -DPROTECTED_MODE_STARTUP
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# If you enable FIXED_AND_VARIABLE it never makes it to the kernel!
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# you have to only enable variable.
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CPUFLAGS += -DENABLE_FIXED_AND_VARIABLE_MTRRS
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CPUFLAGS += -DRAMTEST
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CPUFLAGS += -DUSE_DOC_MIL
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# This makes it fail sooner ...
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#CPUFLAGS += -DINBUF_COPY
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CPUFLAGS += -DCMD_LINE='"ro root=/dev/hda1 console=ttyS0,115200 single "'
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TOP=../..
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INCLUDES=-nostdinc -I $(TOP)/src/include -I $(TOP)/src/arch/i386/include
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NOOPT_CFLAGS=$(INCLUDES) $(CPUFLAGS) -Wall
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CFLAGS=$(NOOPT_CFLAGS) -O2
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OBJECTS=crt0.o hardwaremain.o linuxbiosmain.o
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OBJECTS += mainboard.o mtrr.o subr.o fill_inbuf.o params.o
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OBJECTS += southbridge.o northbridge.o
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#OBJECTS += pci.o
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OBJECTS += printk.o vsprintf.o
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OBJECTS += newpci.o linuxpci.o
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OBJECTS += cpuid.o
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#OBJECTS += intel_irq_tables.o
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OBJECTS += serial_subr.o
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OBJECTS += mpspec.o
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OBJECTS += microcode.o
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OBJECTS += keyboard.o
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OBJECTS += ioapic.o
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LINUX=$(TOP)/../linux-2.4.0-ali/
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LINK = ld -T ldscript.ld -o $@ $(OBJECTS)
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CC=cc $(CFLAGS)
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CCASM=cc -I$(TOP)/chip/intel $(CFLAGS)
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all: romimage
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floppy: all
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mcopy -o romimage a:
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# here's the problem: we shouldn't assume we come up with more than
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# 64K of FLASH up. SO we need a working linuxbios at the tail, and it will
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# enable all flash and then gunzip the linuxbios. As a result,
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# we need the vmlinux.bin.gz padded out and then cat the linuxbios.rom
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# at then end. We always copy it to /tmp so that a waiting root shell
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# can put it on the floppy (see ROOTDOIT)
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romimage: linuxbios.rom vmlinux.bin.gz.block docipl
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cat vmlinux.bin.gz.block linuxbios.rom > romimage
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cp romimage /tmp
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docipl: ipl.o
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objcopy -O binary -R .note -R .comment -S ipl.o adocipl
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dd if=adocipl of=docipl bs=1 skip=1040384
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# I have noe idea why you can not use $(CPUFLAGS) to compile ipl.S
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# a bug with -Di686 ??
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ipl.o: ./ipl.S
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gcc -save-temps -c -I$(TOP)/src/include -I$(TOP)/src $<
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linuxbios.rom: linuxbios.strip mkrom
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./mkrom -s 64 -f -o linuxbios.rom linuxbios.strip
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linuxbios.strip: linuxbios
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objcopy -O binary -R .note -R .comment -S linuxbios linuxbios.strip
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linuxbios: $(OBJECTS) vmlinux.bin.gz
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@rm -f biosobject
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$(LINK)
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nm -n linuxbios > linuxbios.map
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# crt0 actually includes .inc files.
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# For self-documenting purposes, we put the FULL PATH of the
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# .inc files (relative to $TOP/src) in crt0.S.
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# So, for example, earlymtrr.inc is included as cpu/p6/earlymtrr.inc
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# To make this work, add the extra -I $(TOP)/src here.
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crt0.s: $(TOP)/src/mainboard/asus/cua/crt0.S
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$(CCASM) -I $(TOP)/src -E $< > crt0.s
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crt0.o : crt0.s
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$(CCASM) -c crt0.s
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mkrom: $(TOP)/mkrom/mkrom.c
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cc -o mkrom $<
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linuxbiosmain.o: $(TOP)/src/lib/linuxbiosmain.c
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cc $(CFLAGS) -c $<
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mainboard.o: $(TOP)/src/mainboard/asus/cua/mainboard.c
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cc $(CFLAGS) -c $<
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fill_inbuf.o: $(TOP)/src/lib/fill_inbuf.c
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cc $(CFLAGS) -c $<
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params.o: $(TOP)/src/lib/params.c
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cc $(CFLAGS) $(LINUXINCLUDE) -c $<
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ioapic.o: $(TOP)/src/cpu/p6/ioapic.c
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cc $(CFLAGS) $(LINUXINCLUDE) -c $<
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hardwaremain.o: $(TOP)/src/lib/hardwaremain.c
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cc $(CFLAGS) -c $<
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southbridge.o: $(TOP)/src/southbridge/acer/m1535/southbridge.c
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cc $(CFLAGS) -c $<
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northbridge.o: $(TOP)/src/northbridge/acer/m1631/northbridge.c
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cc $(CFLAGS) -c $<
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pci.o: $(TOP)/src/lib/pci.c
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cc $(CFLAGS) -c $<
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# not on this machine, not yet.
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#intel_irq_tables.o: ../../chip/intel/intel_irq_tables.c
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# cc $(CFLAGS) -o $@ -c $<
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mtrr.o: $(TOP)/src/cpu/p6/mtrr.c
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cc $(CFLAGS) -c $<
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subr.o: $(TOP)/src/lib/subr.c
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cc $(CFLAGS) -c $<
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keyboard.o: $(TOP)/src/pc80/keyboard.c
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cc $(CFLAGS) -c $<
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cpuid.o: $(TOP)/src/cpu/p5/cpuid.c
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cc $(CFLAGS) -c $<
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mpspec.o: $(TOP)/src/cpu/p6/mpspec.c
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$(CC) $(CFLAGS) -c $<
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microcode.o: $(TOP)/src/cpu/p6/microcode.c
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$(CC) $(CFLAGS) -c $<
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serial_subr.o: $(TOP)/src/lib/serial_subr.c
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cc $(CFLAGS) -c $<
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printk.o: $(TOP)/src/lib/printk.c
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cc $(CFLAGS) -c $<
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vsprintf.o: $(TOP)/src/lib/vsprintf.c
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cc $(CFLAGS) -c $<
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newpci.o: $(TOP)/src/lib/newpci.c
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cc $(CFLAGS) -c $<
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linuxpci.o: $(TOP)/src/lib/linuxpci.c
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cc $(CFLAGS) -c $<
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vmlinux.bin.gz.block: vmlinux.bin.gz
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dd conv=sync bs=448k if=vmlinux.bin.gz of=vmlinux.bin.gz.block
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vmlinux.bin.gz: vmlinux.bin
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gzip -f -3 vmlinux.bin
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vmlinux.bin: $(LINUX)/vmlinux
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objcopy -O binary -R .note -R .comment -S $< vmlinux.bin
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alltags:
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gctags ../inflate/*.c ../../lib/*.c ../../chip/intel/*.c
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etags ../inflate/*.c ../../lib/*.c ../../chip/intel/*.c
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clean::
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rm -f linuxbios.* vmlinux.* *.o mkrom xa? *~ linuxbios romimage crt0.s
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rm -f a.out *.s *.l
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rm -f TAGS tags
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438
romimages/RON_ASUS_CUA_DOC2/ipl.S
Normal file
438
romimages/RON_ASUS_CUA_DOC2/ipl.S
Normal file
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@ -0,0 +1,438 @@
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/*
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This software and ancillary information (herein called SOFTWARE )
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called LinuxBIOS is made available under the terms described
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here. The SOFTWARE has been approved for release with associated
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LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has
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been authored by an employee or employees of the University of
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California, operator of the Los Alamos National Laboratory under
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Contract No. W-7405-ENG-36 with the U.S. Department of Energy. The
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U.S. Government has rights to use, reproduce, and distribute this
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SOFTWARE. The public may copy, distribute, prepare derivative works
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and publicly display this SOFTWARE without charge, provided that this
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Notice and any statement of authorship are reproduced on all copies.
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Neither the Government nor the University makes any warranty, express
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or implied, or assumes any liability or responsibility for the use of
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this SOFTWARE. If SOFTWARE is modified to produce derivative works,
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such modified SOFTWARE should be clearly marked, so as not to confuse
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it with the version available from LANL.
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*/
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/* Parts of this code Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL
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* rminnich@lanl.gov
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* Modifications by Ronnie Liu of Acer Labs Inc.
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*/
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#include <asm.h>
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#include <cpu/p5/macros.h>
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#define DOC_WIN_SEG 0xfe00
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#define DOC_STACK_SEG 0x0400
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#define SPL_RAM_SEG 0x8000
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#define DOC_SPL_START_BLK 2 /* 0,1 for IPL */
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#define DOC_SPL_SIZE_IN_PAGE 126 /* 1 page = 512 bytes, total 63kB */
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/* wow, the usual way to to this hurts. So we do it our way:
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* 32-bit test not needed.
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*/
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/* the MCR is 32-bits. You set it, it programs SDRAM.
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* first check: get Column address size (CAS)
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* Start out assuming that it is 8 bits, then grow.
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* nicely, if we put the 32-bit MCR value in %ecs, we can
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* ror it 16 bits, and as we grow the CAS, we just inc cs, and that will
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* set the right value.
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*/
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#define INIT_MCR $0xf6411000
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#define WRITE_MCR0 movl %ecx, %eax ; outl %eax, %dx
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/*#include <cpu/p5/start32.inc>*/
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.org 0xfe000
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.code16
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_start: jmp _realstart
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gdt: //GDT entry 0 (null segment)
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.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
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.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
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// GDT 1
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.word 0xffff, 0x0000 /* flat code segment */
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.byte 0x0, 0x9a, 0xcf, 0x0
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.word 0xffff, 0x0000 /* flat data segment */
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.byte 0x0, 0x92, 0xcf, 0x0
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gdtptr:
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.word 4*8-1
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.long gdt /* we know the offset */
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.long 0
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#define DO_INB 1
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#define NO_INB 0
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bytes:
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.byte 0xf8, 0xfd, NO_INB, 0x8
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.byte 0x8c, 0xfe, DO_INB, 0x8
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.byte 0x48, 0xfd, NO_INB, 0x60
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.byte 0x80, 0xfe, NO_INB, 0x10
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.byte 0x90, 0xff, DO_INB, 0x6
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.byte 0x80, 0xff, NO_INB, 0
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.byte 0
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_realstart:
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cli
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movw %cs, %ax
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movw %ax, %es
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.byte 0x66 /* prefix */
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.byte 0x26
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.byte 0x0f, 0x01, 0x16 /* lgdt [es:offset]*/
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.word gdtptr - EXT(_start) /* offset in segment */
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movl %cr0, %eax
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andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
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orl $0x60000001, %eax /* CD, NW, PE = 1 */
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movl %eax, %cr0
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/* invalidate the cache */
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invd
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data32 ljmp $0x10, $.Lprotected
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.Lprotected:
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.code32
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movw $0x18, %bx
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movw %bx, %es
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movw %bx, %ds
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movw %bx, %es
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movw %bx, %fs
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movw %bx, %gs
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movw %bx, %ss
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#ifdef USE_BIG_REAL
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andb $0xfe, %al
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movl %eax, %cr0
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ljmp $0xfe00, $.Lunprotected
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Lunprotected:
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code16
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#endif
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/* make the flash writeable */
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/* select the south bridge, register 44 (base) */
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/* south bridge is device 7. 7 << 3 is 0x38 */
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movl $0x80003844, %eax
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mov $0x0cf8,%dx
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outl %eax,%dx
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/* but 0x40 makes flash writeable. You need this for DoC */
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movb $0x40, %al
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/* 0xff selects register 0x47 */
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movb $0xff, %dl
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outb %al,%dx
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xorl %edi, %edi
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xorw %ax,%ax
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movl $bytes, %esi
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/* Must set regs on North Bridge */
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movb $0xc, %dh
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movb (%esi), %al
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loop:
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movb $0xf8, %dl
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inc %esi
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outl %eax,%dx
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movb (%esi),%dl
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inc %esi
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movb (%esi),%al
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// if there is a zero, then you do an inb
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// the reason to do it this way is so the orb will be
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// always working: either orb with 0 (no inb)
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// or orb with the result of the inb (inb replaces the 0)
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cmpb $NO_INB, %al
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jz noinb
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inb %dx, %al
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noinb:
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inc %esi
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orb (%esi), %al
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outb %al,%dx
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inc %esi
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movb (%esi), %al
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cmpb $0, %al
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jne loop
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movb $0x6c, %al
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movb $0xf8,%dl
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outl %eax,%dx
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/* movb $0x8000006c, %al
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CALLSP(pci_read_dword)*/
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movb $0xfc, %dl
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inl %dx, %eax
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movl %eax, %ecx
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andl $0xfffc, %ecx
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orl INIT_MCR, %ecx
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WRITE_MCR0
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/*
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movb $0x6c, %al
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CALLSP(pci_write_dword)
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*/
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rorl $16, %ecx
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/* clear out the CAS, since we assume start at zero
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* and increment
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*/
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andb $0xf0, %cl
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/* test 8 bit CAS */
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movb $0, 0
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movb $1, 0x800
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cmpb $0,0
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jnz sizeram
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inc %cl
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/* change the value we store each time. It makes debugging easier */
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movb $2, 0x1000
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cmpb $0, 0
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jnz sizeram
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inc %cl
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movb $3, 0x2000
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cmpb $0, 0
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jnz sizeram
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inc %cl
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sizeram:
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rorl $16, %ecx
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/* clear the 'no multi page' bit. */
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andw $0xefff, %cx
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WRITE_MCR0
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/*
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mov $0x6c, %al
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CALLSP(pci_write_dword)
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*/
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/* size is now in cx[19:16] */
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/* now size the dram */
|
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/* you had best have at least 4M; that's as small as we go */
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/* rorr 20 the ecx value, to get row size into lsb */
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movb $0, 0
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ror $20, %ecx
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/* clear the size out to 4 MB */
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andb $0xf8, %cl
|
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/* 4 MB */
|
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movl $0x400000, %esi
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1:
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#ifdef USE_BIG_REAL
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addr32 movb $4, %es:(%esi)
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#else
|
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/* move a 4 to the next power-of-two address.
|
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* if there is no memory there, it will wrap to zero
|
||||
*/
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movb $4, %es:(%esi)
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||||
#endif
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||||
cmpb $0, 0
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||||
/* if there is not a 0 at 0, the last write wrapped. Hop out */
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jne 1f
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inc %cl
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||||
rol $1, %esi
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jmp 1b
|
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/* size is now in esi */
|
||||
/* %ecx has setting for register */
|
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1:
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rol $20, %ecx
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/* set 4 banks. */
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orb $1, %cl
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WRITE_MCR0
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/*
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||||
mov $0x6c, %al
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CALLSP(pci_write_dword)
|
||||
*/
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||||
/* bank detect */
|
||||
/* you don't need to even care how large CAS is.
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||||
* Just set 4-bank mode, and set non-zero numbers into a few places.
|
||||
* if the byte at 0 changes, you have two banks. Trivial.
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||||
*/
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movb $0, 0
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movb $5, 0x1000
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movb $6, 0x2000
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movb $7, 0x4000
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cmpb $0, 0
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jz 1f /* only one bank */
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orl $0x80000, %ecx
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1:
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/* clear 4 banks */
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andb $0xfe, %cl
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WRITE_MCR0
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movl $0x8000007c, %eax
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movb $0xf8, %dl
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outl %eax, %dx
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movl $0x242bc411, %eax
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movb $0xfc, %dl
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outl %eax, %dx
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/*
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mov $0x6c, %al
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CALLSP(pci_write_dword)
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*/
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||||
/* at this point, dram slot 0 is up. we hope. */
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||||
|
||||
/* now for flash ... */
|
||||
/* NOTE: MUST NOT DESTROY %ecx! */
|
||||
/* INPUT: %al, the register. %ecx, the write data */
|
||||
/* Following code courtesy Ollie Lho: */
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
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/*
|
||||
* ipl.S: Initial Program Loader (IPL) for SiS 630 and M-System DoC Millennium
|
||||
*
|
||||
*
|
||||
* Copyright 2000 Silicon Integrated Systems Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
*
|
||||
* Reference:
|
||||
* 1. SiS 630 Specification
|
||||
* 2. System Management Bus Specification Rev 1.1
|
||||
* 3. PC SDRAM Serial Presence Detect (SPD) Specification Rev 1.2B
|
||||
* 4. Booting From the DiskOnChip Millennium, M-Systems Application Note Ap-DOC-044
|
||||
* APR-2000, 93-SR-001-44-7L REV. 1.0
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
#define DOC_WIN_SEG 0xfe00
|
||||
#define DOC_STACK 0x04000
|
||||
#define SPL_RAM 0x80000
|
||||
|
||||
#define DOC_SPL_START_BLK 2 /* 0,1 for IPL */
|
||||
#define DOC_SPL_SIZE_IN_PAGE 126 /* 1 page = 512 bytes, total 63kB */
|
||||
|
||||
ipl_start:
|
||||
#if 0
|
||||
/* stack and es already set. */
|
||||
/* O.K. we have DRAM now, so set up STACK for CALL/RET */
|
||||
movw $DOC_STACK_SEG, %ax
|
||||
movw %ax, %ss
|
||||
movw $SPL_RAM_SEG, %ax
|
||||
movw %ax, %es
|
||||
movl $DOC_STACK_SEG, %esp # set %sp
|
||||
#endif
|
||||
/* NOTE: in ollie's original code, %ds was at 0xfe00, i.e.
|
||||
* 0xfe000, i.e. base of DoC. We have to adjust for that when
|
||||
* we set %edi and %esi
|
||||
*/
|
||||
movl $DOC_STACK, %esp # set %sp
|
||||
movl $SPL_RAM, %edx # start of RAM
|
||||
xorl %ecx, %ecx # clear %ecx
|
||||
movl $0xfe800, %esi # point %si to CDSN Data area
|
||||
movl $0xff000, %edi # point %di to CDSN Control area
|
||||
movl $DOC_SPL_START_BLK, %ebp # start page of LinuxBIOS
|
||||
|
||||
movb $0x84, %al # Reset DOC Millennium
|
||||
call doc_reset
|
||||
|
||||
movb $0x85, %al # Turn into Normal Mode
|
||||
call doc_reset
|
||||
|
||||
read_next_page:
|
||||
movl $0xff000, %edi # point %di to CDSN Control area
|
||||
|
||||
flash_command:
|
||||
movb $0x03, 0x04(%edi) # start command cycle
|
||||
movb $0x00, (%esi) # issue flash command Read00
|
||||
call doc_cycle_end
|
||||
|
||||
movw %bp, %bx # %bp is current page number
|
||||
|
||||
flash_address:
|
||||
shll $0x08, %ebx
|
||||
movb $0x03, %cl # this one is DANGEROUS but I am
|
||||
# sure the upper 3 bytes == 0x00
|
||||
|
||||
movb $0x05, 0x04(%edi) # start address cycle
|
||||
0:
|
||||
movb %bl, (%esi) # write address to CDSNIO
|
||||
shrw $0x08, %bx # shift next address byte
|
||||
loop 0b
|
||||
|
||||
call doc_cycle_end
|
||||
|
||||
wait_for_flash_ready:
|
||||
/* delay by reding NOP register before polling the FLASH READY bit,
|
||||
this is inlined to save a call/ret pair */
|
||||
doc_delay:
|
||||
movb $0x04, %cl # this one is DANGEROUS but I am
|
||||
# sure the upper 3 bytes == 0x00
|
||||
0:
|
||||
movb 0x20(%edi), %al # read DOC NOP retisger
|
||||
loop 0b # four times
|
||||
|
||||
testb $0x80, 0x04(%edi) # is flash ready ?
|
||||
jz wait_for_flash_ready
|
||||
|
||||
movb 0x1d(%edi), %al # init read pipeline
|
||||
movw $0x100, %cx # 1 page = 512 bytes
|
||||
movl $0xfe800, %esi # point %si to CDSN Data area
|
||||
movl %edx, %edi # restore saved current destination
|
||||
rep
|
||||
movsw
|
||||
|
||||
movl %edi, %edx # save current destination
|
||||
incw %bp # increse current page number
|
||||
cmpw $128, %bp # moved 63 KB ??
|
||||
jl read_next_page # no, read next page
|
||||
|
||||
sis630ipl_end:
|
||||
# jmp to 8000:0000, where SPL
|
||||
# (LinuxBIOS) starts in RAM
|
||||
# ljmp $0x10,$0x8000
|
||||
jmp spl_vector
|
||||
|
||||
doc_reset:
|
||||
/* Input: AL = value write to DOC_CONTROL register
|
||||
Clobberd: CX */
|
||||
movb %al, 0x02(%edi) # write DoC Control retister
|
||||
movb %al, 0x02(%edi) # twice
|
||||
ret # End of doc_reset
|
||||
|
||||
doc_cycle_end:
|
||||
movb $0x00, 0x1e(%edi) # flush write pepeline
|
||||
movb $0x01, 0x04(%edi) # end command cycle
|
||||
ret
|
||||
|
||||
|
||||
/* we don't need these. We only do I/O to MCR 0 */
|
||||
pci_write_dword:
|
||||
mov $0,%ah
|
||||
mov $0x80000000,%edx
|
||||
or %ax,%dx
|
||||
mov %edx,%eax
|
||||
mov $0x0cf8,%dx
|
||||
outl %eax,%dx
|
||||
mov $0x0fc,%dl
|
||||
mov %ecx, %eax
|
||||
outl %eax,%dx
|
||||
RETSP
|
||||
pci_read_dword:
|
||||
mov $0,%ah
|
||||
mov $0x80000000,%edx
|
||||
or %ax,%dx
|
||||
mov %edx,%eax
|
||||
mov $0x0cf8,%dx
|
||||
outl %eax,%dx
|
||||
mov $0x0fc,%dl
|
||||
inl %dx, %eax
|
||||
mov %eax, %ecx
|
||||
RETSP
|
||||
|
||||
.org 0xfe1f0
|
||||
reset_vector:
|
||||
.byte 0xea # jmp to fe00:0000, where IPL
|
||||
.word 0x0000, DOC_WIN_SEG # starts in DoC
|
||||
.code32
|
||||
spl_vector:
|
||||
invd
|
||||
jmpl $0x10, $0x80000
|
||||
# jmpl $0x80000
|
||||
# put this here to buy some room!
|
||||
pad: .byte 0,0
|
||||
|
||||
114
romimages/RON_ASUS_CUA_DOC2/ldscript.ld
Normal file
114
romimages/RON_ASUS_CUA_DOC2/ldscript.ld
Normal file
|
|
@ -0,0 +1,114 @@
|
|||
/*
|
||||
* Bootstrap code for the STPC Consumer
|
||||
* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
|
||||
*
|
||||
* $Id$
|
||||
*
|
||||
*/
|
||||
/* oh, barf. This won't work if all you use is .o's. -- RGM */
|
||||
|
||||
/*
|
||||
* Written by Johan Rydberg, based on work by Daniel Kahlin.
|
||||
*/
|
||||
/*
|
||||
* We use ELF as output format. So that we can
|
||||
* debug the code in some form.
|
||||
*/
|
||||
OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
|
||||
OUTPUT_ARCH(i386)
|
||||
|
||||
/*
|
||||
* Memory map:
|
||||
*
|
||||
* 0x00000 (4*4096 bytes) : stack
|
||||
* 0x04000 (4096 bytes) : private data
|
||||
* 0x05000 : data space
|
||||
* 0x90000 : kernel stack
|
||||
* 0xf0000 (64 Kbyte) : EPROM
|
||||
*/
|
||||
MEMORY
|
||||
{
|
||||
ram (rwx) : ORIGIN = 0x00000000, LENGTH = 128M /* 128 MB memory is max for STPC */
|
||||
rom (rx) : ORIGIN = 0x000f0000, LENGTH = 128K /* 128 K EPROM */
|
||||
}
|
||||
|
||||
_PDATABASE = 0x04000;
|
||||
_RAMBASE = 0x05000;
|
||||
_KERNSTK = 0x90000;
|
||||
|
||||
/* should be parameterized but is not, yuck! */
|
||||
_ROMBASE = 0x80000;
|
||||
|
||||
/*
|
||||
* Entry point is not really nececary, since the mkrom(8)
|
||||
* tool creates a entry point that jumps to $0xc000:0x0000.
|
||||
*/
|
||||
/* baloney, but ... RGM*/
|
||||
ENTRY(_start)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/*
|
||||
* First we place the code and read only data (typically const declared).
|
||||
* This get placed in rom.
|
||||
*/
|
||||
.text _ROMBASE : {
|
||||
_text = .;
|
||||
*(.text);
|
||||
*(.rodata);
|
||||
_etext = .;
|
||||
}
|
||||
|
||||
_pdata = .;
|
||||
|
||||
/*
|
||||
.pdata _PDATABASE : AT ( LOADADDR(.text) + SIZEOF(.text) +
|
||||
SIZEOF(.rodata)) {
|
||||
*/
|
||||
.pdata _PDATABASE : AT ( _etext ) {
|
||||
*(.pdata);
|
||||
}
|
||||
|
||||
_epdata = LOADADDR(.pdata) + SIZEOF(.pdata);
|
||||
|
||||
/*
|
||||
* After the code we place initialized data (typically initialized
|
||||
* global variables). This gets copied into ram by startup code.
|
||||
* __data_start and __data_end shows where in ram this should be placed,
|
||||
* whereas __data_loadstart and __data_loadend shows where in rom to
|
||||
* copy from.
|
||||
*/
|
||||
.data _RAMBASE : AT ( LOADADDR(.pdata) + SIZEOF(.pdata) ) {
|
||||
_data = .;
|
||||
*(.data)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.got)
|
||||
_edata = .;
|
||||
}
|
||||
|
||||
_ldata = LOADADDR(.data);
|
||||
_eldata = LOADADDR(.data) + SIZEOF(.data);
|
||||
|
||||
/*
|
||||
* bss does not contain data, it is just a space that should be zero
|
||||
* initialized on startup. (typically uninitialized global variables)
|
||||
* crt0.S fills between __bss_start and __bss_end with zeroes.
|
||||
*/
|
||||
.bss ( ADDR(.data) + SIZEOF(.data) ) : {
|
||||
_bss = .;
|
||||
*(.bss)
|
||||
*(.sbss)
|
||||
*(COMMON)
|
||||
_ebss = .;
|
||||
_heap = .;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* This provides the start and end address for the whole image
|
||||
*/
|
||||
_image = LOADADDR(.text);
|
||||
_eimage = LOADADDR(.data) + SIZEOF(.data);
|
||||
|
||||
/* EOF */
|
||||
2712
src/kernel_patches/linux-2.4.2-SiS.patch
Normal file
2712
src/kernel_patches/linux-2.4.2-SiS.patch
Normal file
File diff suppressed because it is too large
Load diff
Loading…
Add table
Reference in a new issue