diff --git a/romimages/RON_ASUS_CUA_DOC2/Makefile b/romimages/RON_ASUS_CUA_DOC2/Makefile new file mode 100644 index 0000000000..e3afe47038 --- /dev/null +++ b/romimages/RON_ASUS_CUA_DOC2/Makefile @@ -0,0 +1,174 @@ +CPUFLAGS=-Di386 -Di486 -Di686 -Di586 +# Well, we have old silicon +CPUFLAGS += -DINTEL_BRIDGE_CONFIG +CPUFLAGS += -DINTEL_PPRO_MTRR +CPUFLAGS += -DNEWPCI +CPUFLAGS += -DSERIAL_CONSOLE +CPUFLAGS += -DFINAL_MAINBOARD_FIXUP +CPUFLAGS += -DPROTECTED_MODE_STARTUP +# If you enable FIXED_AND_VARIABLE it never makes it to the kernel! +# you have to only enable variable. +CPUFLAGS += -DENABLE_FIXED_AND_VARIABLE_MTRRS +CPUFLAGS += -DRAMTEST +CPUFLAGS += -DUSE_DOC_MIL +# This makes it fail sooner ... +#CPUFLAGS += -DINBUF_COPY +CPUFLAGS += -DCMD_LINE='"ro root=/dev/hda1 console=ttyS0,115200 single "' + +TOP=../.. +INCLUDES=-nostdinc -I $(TOP)/src/include -I $(TOP)/src/arch/i386/include +NOOPT_CFLAGS=$(INCLUDES) $(CPUFLAGS) -Wall +CFLAGS=$(NOOPT_CFLAGS) -O2 + +OBJECTS=crt0.o hardwaremain.o linuxbiosmain.o +OBJECTS += mainboard.o mtrr.o subr.o fill_inbuf.o params.o +OBJECTS += southbridge.o northbridge.o +#OBJECTS += pci.o +OBJECTS += printk.o vsprintf.o +OBJECTS += newpci.o linuxpci.o +OBJECTS += cpuid.o +#OBJECTS += intel_irq_tables.o +OBJECTS += serial_subr.o +OBJECTS += mpspec.o +OBJECTS += microcode.o +OBJECTS += keyboard.o +OBJECTS += ioapic.o +LINUX=$(TOP)/../linux-2.4.0-ali/ + +LINK = ld -T ldscript.ld -o $@ $(OBJECTS) +CC=cc $(CFLAGS) +CCASM=cc -I$(TOP)/chip/intel $(CFLAGS) + +all: romimage +floppy: all + mcopy -o romimage a: +# here's the problem: we shouldn't assume we come up with more than +# 64K of FLASH up. SO we need a working linuxbios at the tail, and it will +# enable all flash and then gunzip the linuxbios. As a result, +# we need the vmlinux.bin.gz padded out and then cat the linuxbios.rom +# at then end. We always copy it to /tmp so that a waiting root shell +# can put it on the floppy (see ROOTDOIT) +romimage: linuxbios.rom vmlinux.bin.gz.block docipl + cat vmlinux.bin.gz.block linuxbios.rom > romimage + cp romimage /tmp + +docipl: ipl.o + objcopy -O binary -R .note -R .comment -S ipl.o adocipl + dd if=adocipl of=docipl bs=1 skip=1040384 + +# I have noe idea why you can not use $(CPUFLAGS) to compile ipl.S +# a bug with -Di686 ?? +ipl.o: ./ipl.S + gcc -save-temps -c -I$(TOP)/src/include -I$(TOP)/src $< + +linuxbios.rom: linuxbios.strip mkrom + ./mkrom -s 64 -f -o linuxbios.rom linuxbios.strip + +linuxbios.strip: linuxbios + objcopy -O binary -R .note -R .comment -S linuxbios linuxbios.strip + +linuxbios: $(OBJECTS) vmlinux.bin.gz + @rm -f biosobject + $(LINK) + nm -n linuxbios > linuxbios.map + +# crt0 actually includes .inc files. +# For self-documenting purposes, we put the FULL PATH of the +# .inc files (relative to $TOP/src) in crt0.S. +# So, for example, earlymtrr.inc is included as cpu/p6/earlymtrr.inc +# To make this work, add the extra -I $(TOP)/src here. +crt0.s: $(TOP)/src/mainboard/asus/cua/crt0.S + $(CCASM) -I $(TOP)/src -E $< > crt0.s + +crt0.o : crt0.s + $(CCASM) -c crt0.s + +mkrom: $(TOP)/mkrom/mkrom.c + cc -o mkrom $< + +linuxbiosmain.o: $(TOP)/src/lib/linuxbiosmain.c + cc $(CFLAGS) -c $< + +mainboard.o: $(TOP)/src/mainboard/asus/cua/mainboard.c + cc $(CFLAGS) -c $< + +fill_inbuf.o: $(TOP)/src/lib/fill_inbuf.c + cc $(CFLAGS) -c $< + +params.o: $(TOP)/src/lib/params.c + cc $(CFLAGS) $(LINUXINCLUDE) -c $< + +ioapic.o: $(TOP)/src/cpu/p6/ioapic.c + cc $(CFLAGS) $(LINUXINCLUDE) -c $< + +hardwaremain.o: $(TOP)/src/lib/hardwaremain.c + cc $(CFLAGS) -c $< + +southbridge.o: $(TOP)/src/southbridge/acer/m1535/southbridge.c + cc $(CFLAGS) -c $< + +northbridge.o: $(TOP)/src/northbridge/acer/m1631/northbridge.c + cc $(CFLAGS) -c $< + +pci.o: $(TOP)/src/lib/pci.c + cc $(CFLAGS) -c $< + +# not on this machine, not yet. +#intel_irq_tables.o: ../../chip/intel/intel_irq_tables.c +# cc $(CFLAGS) -o $@ -c $< + +mtrr.o: $(TOP)/src/cpu/p6/mtrr.c + cc $(CFLAGS) -c $< + +subr.o: $(TOP)/src/lib/subr.c + cc $(CFLAGS) -c $< + +keyboard.o: $(TOP)/src/pc80/keyboard.c + cc $(CFLAGS) -c $< + +cpuid.o: $(TOP)/src/cpu/p5/cpuid.c + cc $(CFLAGS) -c $< + +mpspec.o: $(TOP)/src/cpu/p6/mpspec.c + $(CC) $(CFLAGS) -c $< + +microcode.o: $(TOP)/src/cpu/p6/microcode.c + $(CC) $(CFLAGS) -c $< + +serial_subr.o: $(TOP)/src/lib/serial_subr.c + cc $(CFLAGS) -c $< + +printk.o: $(TOP)/src/lib/printk.c + cc $(CFLAGS) -c $< + +vsprintf.o: $(TOP)/src/lib/vsprintf.c + cc $(CFLAGS) -c $< + +newpci.o: $(TOP)/src/lib/newpci.c + cc $(CFLAGS) -c $< + +linuxpci.o: $(TOP)/src/lib/linuxpci.c + cc $(CFLAGS) -c $< + +vmlinux.bin.gz.block: vmlinux.bin.gz + dd conv=sync bs=448k if=vmlinux.bin.gz of=vmlinux.bin.gz.block +vmlinux.bin.gz: vmlinux.bin + gzip -f -3 vmlinux.bin + +vmlinux.bin: $(LINUX)/vmlinux + objcopy -O binary -R .note -R .comment -S $< vmlinux.bin + +alltags: + gctags ../inflate/*.c ../../lib/*.c ../../chip/intel/*.c + etags ../inflate/*.c ../../lib/*.c ../../chip/intel/*.c + + +clean:: + rm -f linuxbios.* vmlinux.* *.o mkrom xa? *~ linuxbios romimage crt0.s + rm -f a.out *.s *.l + rm -f TAGS tags + + + + + diff --git a/romimages/RON_ASUS_CUA_DOC2/ipl.S b/romimages/RON_ASUS_CUA_DOC2/ipl.S new file mode 100644 index 0000000000..27c2be813f --- /dev/null +++ b/romimages/RON_ASUS_CUA_DOC2/ipl.S @@ -0,0 +1,438 @@ +/* +This software and ancillary information (herein called SOFTWARE ) +called LinuxBIOS is made available under the terms described +here. The SOFTWARE has been approved for release with associated +LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has +been authored by an employee or employees of the University of +California, operator of the Los Alamos National Laboratory under +Contract No. W-7405-ENG-36 with the U.S. Department of Energy. The +U.S. Government has rights to use, reproduce, and distribute this +SOFTWARE. The public may copy, distribute, prepare derivative works +and publicly display this SOFTWARE without charge, provided that this +Notice and any statement of authorship are reproduced on all copies. +Neither the Government nor the University makes any warranty, express +or implied, or assumes any liability or responsibility for the use of +this SOFTWARE. If SOFTWARE is modified to produce derivative works, +such modified SOFTWARE should be clearly marked, so as not to confuse +it with the version available from LANL. + */ +/* Parts of this code Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL + * rminnich@lanl.gov + * Modifications by Ronnie Liu of Acer Labs Inc. + */ +#include +#include +#define DOC_WIN_SEG 0xfe00 +#define DOC_STACK_SEG 0x0400 +#define SPL_RAM_SEG 0x8000 + +#define DOC_SPL_START_BLK 2 /* 0,1 for IPL */ +#define DOC_SPL_SIZE_IN_PAGE 126 /* 1 page = 512 bytes, total 63kB */ + +/* wow, the usual way to to this hurts. So we do it our way: + * 32-bit test not needed. + */ +/* the MCR is 32-bits. You set it, it programs SDRAM. + * first check: get Column address size (CAS) + * Start out assuming that it is 8 bits, then grow. + * nicely, if we put the 32-bit MCR value in %ecs, we can + * ror it 16 bits, and as we grow the CAS, we just inc cs, and that will + * set the right value. + */ +#define INIT_MCR $0xf6411000 +#define WRITE_MCR0 movl %ecx, %eax ; outl %eax, %dx +/*#include */ +.org 0xfe000 +.code16 +_start: jmp _realstart +gdt: //GDT entry 0 (null segment) + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 + // GDT 1 + .word 0xffff, 0x0000 /* flat code segment */ + .byte 0x0, 0x9a, 0xcf, 0x0 + + .word 0xffff, 0x0000 /* flat data segment */ + .byte 0x0, 0x92, 0xcf, 0x0 + +gdtptr: + .word 4*8-1 + .long gdt /* we know the offset */ + .long 0 +#define DO_INB 1 +#define NO_INB 0 +bytes: + .byte 0xf8, 0xfd, NO_INB, 0x8 + .byte 0x8c, 0xfe, DO_INB, 0x8 + .byte 0x48, 0xfd, NO_INB, 0x60 + .byte 0x80, 0xfe, NO_INB, 0x10 + .byte 0x90, 0xff, DO_INB, 0x6 + .byte 0x80, 0xff, NO_INB, 0 + .byte 0 +_realstart: + + cli + movw %cs, %ax + movw %ax, %es + + + .byte 0x66 /* prefix */ + .byte 0x26 + .byte 0x0f, 0x01, 0x16 /* lgdt [es:offset]*/ + .word gdtptr - EXT(_start) /* offset in segment */ + + movl %cr0, %eax + andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */ + orl $0x60000001, %eax /* CD, NW, PE = 1 */ + movl %eax, %cr0 + + /* invalidate the cache */ + invd + data32 ljmp $0x10, $.Lprotected + +.Lprotected: + .code32 + movw $0x18, %bx + movw %bx, %es + movw %bx, %ds + movw %bx, %es + movw %bx, %fs + movw %bx, %gs + movw %bx, %ss +#ifdef USE_BIG_REAL + andb $0xfe, %al + movl %eax, %cr0 + ljmp $0xfe00, $.Lunprotected +Lunprotected: +code16 +#endif + +/* make the flash writeable */ +/* select the south bridge, register 44 (base) */ +/* south bridge is device 7. 7 << 3 is 0x38 */ + movl $0x80003844, %eax + mov $0x0cf8,%dx + outl %eax,%dx +/* but 0x40 makes flash writeable. You need this for DoC */ + movb $0x40, %al +/* 0xff selects register 0x47 */ + movb $0xff, %dl + outb %al,%dx + xorl %edi, %edi + xorw %ax,%ax + movl $bytes, %esi + /* Must set regs on North Bridge */ + movb $0xc, %dh + movb (%esi), %al +loop: + movb $0xf8, %dl + inc %esi + outl %eax,%dx + movb (%esi),%dl + inc %esi + movb (%esi),%al + // if there is a zero, then you do an inb + // the reason to do it this way is so the orb will be + // always working: either orb with 0 (no inb) + // or orb with the result of the inb (inb replaces the 0) + cmpb $NO_INB, %al + jz noinb + inb %dx, %al +noinb: + inc %esi + orb (%esi), %al + outb %al,%dx + inc %esi + movb (%esi), %al + cmpb $0, %al + jne loop + + + movb $0x6c, %al + movb $0xf8,%dl + outl %eax,%dx +/* movb $0x8000006c, %al + CALLSP(pci_read_dword)*/ + movb $0xfc, %dl + inl %dx, %eax + movl %eax, %ecx + andl $0xfffc, %ecx + orl INIT_MCR, %ecx + WRITE_MCR0 + /* + movb $0x6c, %al + CALLSP(pci_write_dword) + */ + rorl $16, %ecx + /* clear out the CAS, since we assume start at zero + * and increment + */ + andb $0xf0, %cl + /* test 8 bit CAS */ + movb $0, 0 + movb $1, 0x800 + cmpb $0,0 + jnz sizeram + inc %cl + /* change the value we store each time. It makes debugging easier */ + movb $2, 0x1000 + cmpb $0, 0 + jnz sizeram + inc %cl + movb $3, 0x2000 + cmpb $0, 0 + jnz sizeram + inc %cl + +sizeram: + rorl $16, %ecx + /* clear the 'no multi page' bit. */ + andw $0xefff, %cx + WRITE_MCR0 + /* + mov $0x6c, %al + CALLSP(pci_write_dword) + */ +/* size is now in cx[19:16] */ +/* now size the dram */ +/* you had best have at least 4M; that's as small as we go */ +/* rorr 20 the ecx value, to get row size into lsb */ + movb $0, 0 + ror $20, %ecx + /* clear the size out to 4 MB */ + andb $0xf8, %cl + /* 4 MB */ + movl $0x400000, %esi +1: +#ifdef USE_BIG_REAL + addr32 movb $4, %es:(%esi) +#else + /* move a 4 to the next power-of-two address. + * if there is no memory there, it will wrap to zero + */ + movb $4, %es:(%esi) +#endif + cmpb $0, 0 + /* if there is not a 0 at 0, the last write wrapped. Hop out */ + jne 1f + inc %cl + rol $1, %esi + jmp 1b +/* size is now in esi */ +/* %ecx has setting for register */ +1: + rol $20, %ecx +/* set 4 banks. */ + orb $1, %cl + WRITE_MCR0 + /* + mov $0x6c, %al + CALLSP(pci_write_dword) + */ +/* bank detect */ +/* you don't need to even care how large CAS is. + * Just set 4-bank mode, and set non-zero numbers into a few places. + * if the byte at 0 changes, you have two banks. Trivial. + */ + movb $0, 0 + movb $5, 0x1000 + movb $6, 0x2000 + movb $7, 0x4000 + cmpb $0, 0 + jz 1f /* only one bank */ + orl $0x80000, %ecx +1: + /* clear 4 banks */ + andb $0xfe, %cl + WRITE_MCR0 + movl $0x8000007c, %eax + movb $0xf8, %dl + outl %eax, %dx + movl $0x242bc411, %eax + movb $0xfc, %dl + outl %eax, %dx + /* + mov $0x6c, %al + CALLSP(pci_write_dword) + */ + /* at this point, dram slot 0 is up. we hope. */ + + /* now for flash ... */ + /* NOTE: MUST NOT DESTROY %ecx! */ + /* INPUT: %al, the register. %ecx, the write data */ + /* Following code courtesy Ollie Lho: */ + + + + + + + + +/* + * ipl.S: Initial Program Loader (IPL) for SiS 630 and M-System DoC Millennium + * + * + * Copyright 2000 Silicon Integrated Systems Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + * Reference: + * 1. SiS 630 Specification + * 2. System Management Bus Specification Rev 1.1 + * 3. PC SDRAM Serial Presence Detect (SPD) Specification Rev 1.2B + * 4. Booting From the DiskOnChip Millennium, M-Systems Application Note Ap-DOC-044 + * APR-2000, 93-SR-001-44-7L REV. 1.0 + * + * $Id$ + */ +#define DOC_WIN_SEG 0xfe00 +#define DOC_STACK 0x04000 +#define SPL_RAM 0x80000 + +#define DOC_SPL_START_BLK 2 /* 0,1 for IPL */ +#define DOC_SPL_SIZE_IN_PAGE 126 /* 1 page = 512 bytes, total 63kB */ + +ipl_start: +#if 0 + /* stack and es already set. */ + /* O.K. we have DRAM now, so set up STACK for CALL/RET */ + movw $DOC_STACK_SEG, %ax + movw %ax, %ss + movw $SPL_RAM_SEG, %ax + movw %ax, %es + movl $DOC_STACK_SEG, %esp # set %sp +#endif + /* NOTE: in ollie's original code, %ds was at 0xfe00, i.e. + * 0xfe000, i.e. base of DoC. We have to adjust for that when + * we set %edi and %esi + */ + movl $DOC_STACK, %esp # set %sp + movl $SPL_RAM, %edx # start of RAM + xorl %ecx, %ecx # clear %ecx + movl $0xfe800, %esi # point %si to CDSN Data area + movl $0xff000, %edi # point %di to CDSN Control area + movl $DOC_SPL_START_BLK, %ebp # start page of LinuxBIOS + + movb $0x84, %al # Reset DOC Millennium + call doc_reset + + movb $0x85, %al # Turn into Normal Mode + call doc_reset + +read_next_page: + movl $0xff000, %edi # point %di to CDSN Control area + +flash_command: + movb $0x03, 0x04(%edi) # start command cycle + movb $0x00, (%esi) # issue flash command Read00 + call doc_cycle_end + + movw %bp, %bx # %bp is current page number + +flash_address: + shll $0x08, %ebx + movb $0x03, %cl # this one is DANGEROUS but I am + # sure the upper 3 bytes == 0x00 + + movb $0x05, 0x04(%edi) # start address cycle +0: + movb %bl, (%esi) # write address to CDSNIO + shrw $0x08, %bx # shift next address byte + loop 0b + + call doc_cycle_end + +wait_for_flash_ready: + /* delay by reding NOP register before polling the FLASH READY bit, + this is inlined to save a call/ret pair */ +doc_delay: + movb $0x04, %cl # this one is DANGEROUS but I am + # sure the upper 3 bytes == 0x00 +0: + movb 0x20(%edi), %al # read DOC NOP retisger + loop 0b # four times + + testb $0x80, 0x04(%edi) # is flash ready ? + jz wait_for_flash_ready + + movb 0x1d(%edi), %al # init read pipeline + movw $0x100, %cx # 1 page = 512 bytes + movl $0xfe800, %esi # point %si to CDSN Data area + movl %edx, %edi # restore saved current destination + rep + movsw + + movl %edi, %edx # save current destination + incw %bp # increse current page number + cmpw $128, %bp # moved 63 KB ?? + jl read_next_page # no, read next page + +sis630ipl_end: + # jmp to 8000:0000, where SPL + # (LinuxBIOS) starts in RAM +# ljmp $0x10,$0x8000 + jmp spl_vector + +doc_reset: + /* Input: AL = value write to DOC_CONTROL register + Clobberd: CX */ + movb %al, 0x02(%edi) # write DoC Control retister + movb %al, 0x02(%edi) # twice + ret # End of doc_reset + +doc_cycle_end: + movb $0x00, 0x1e(%edi) # flush write pepeline + movb $0x01, 0x04(%edi) # end command cycle + ret + + +/* we don't need these. We only do I/O to MCR 0 */ +pci_write_dword: + mov $0,%ah + mov $0x80000000,%edx + or %ax,%dx + mov %edx,%eax + mov $0x0cf8,%dx + outl %eax,%dx + mov $0x0fc,%dl + mov %ecx, %eax + outl %eax,%dx + RETSP +pci_read_dword: + mov $0,%ah + mov $0x80000000,%edx + or %ax,%dx + mov %edx,%eax + mov $0x0cf8,%dx + outl %eax,%dx + mov $0x0fc,%dl + inl %dx, %eax + mov %eax, %ecx + RETSP + + .org 0xfe1f0 +reset_vector: + .byte 0xea # jmp to fe00:0000, where IPL + .word 0x0000, DOC_WIN_SEG # starts in DoC +.code32 +spl_vector: + invd + jmpl $0x10, $0x80000 +# jmpl $0x80000 +# put this here to buy some room! +pad: .byte 0,0 + diff --git a/romimages/RON_ASUS_CUA_DOC2/ldscript.ld b/romimages/RON_ASUS_CUA_DOC2/ldscript.ld new file mode 100644 index 0000000000..9c5739ca14 --- /dev/null +++ b/romimages/RON_ASUS_CUA_DOC2/ldscript.ld @@ -0,0 +1,114 @@ +/* + * Bootstrap code for the STPC Consumer + * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. + * + * $Id$ + * + */ +/* oh, barf. This won't work if all you use is .o's. -- RGM */ + +/* + * Written by Johan Rydberg, based on work by Daniel Kahlin. + */ +/* + * We use ELF as output format. So that we can + * debug the code in some form. + */ +OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") +OUTPUT_ARCH(i386) + +/* + * Memory map: + * + * 0x00000 (4*4096 bytes) : stack + * 0x04000 (4096 bytes) : private data + * 0x05000 : data space + * 0x90000 : kernel stack + * 0xf0000 (64 Kbyte) : EPROM + */ +MEMORY +{ + ram (rwx) : ORIGIN = 0x00000000, LENGTH = 128M /* 128 MB memory is max for STPC */ + rom (rx) : ORIGIN = 0x000f0000, LENGTH = 128K /* 128 K EPROM */ +} + +_PDATABASE = 0x04000; +_RAMBASE = 0x05000; +_KERNSTK = 0x90000; + +/* should be parameterized but is not, yuck! */ +_ROMBASE = 0x80000; + +/* + * Entry point is not really nececary, since the mkrom(8) + * tool creates a entry point that jumps to $0xc000:0x0000. + */ +/* baloney, but ... RGM*/ +ENTRY(_start) + +SECTIONS +{ + /* + * First we place the code and read only data (typically const declared). + * This get placed in rom. + */ + .text _ROMBASE : { + _text = .; + *(.text); + *(.rodata); + _etext = .; + } + + _pdata = .; + +/* + .pdata _PDATABASE : AT ( LOADADDR(.text) + SIZEOF(.text) + + SIZEOF(.rodata)) { + */ + .pdata _PDATABASE : AT ( _etext ) { + *(.pdata); + } + + _epdata = LOADADDR(.pdata) + SIZEOF(.pdata); + + /* + * After the code we place initialized data (typically initialized + * global variables). This gets copied into ram by startup code. + * __data_start and __data_end shows where in ram this should be placed, + * whereas __data_loadstart and __data_loadend shows where in rom to + * copy from. + */ + .data _RAMBASE : AT ( LOADADDR(.pdata) + SIZEOF(.pdata) ) { + _data = .; + *(.data) + *(.sdata) + *(.sdata2) + *(.got) + _edata = .; + } + + _ldata = LOADADDR(.data); + _eldata = LOADADDR(.data) + SIZEOF(.data); + + /* + * bss does not contain data, it is just a space that should be zero + * initialized on startup. (typically uninitialized global variables) + * crt0.S fills between __bss_start and __bss_end with zeroes. + */ + .bss ( ADDR(.data) + SIZEOF(.data) ) : { + _bss = .; + *(.bss) + *(.sbss) + *(COMMON) + _ebss = .; + _heap = .; + } +} + +/* + * This provides the start and end address for the whole image + */ +_image = LOADADDR(.text); +_eimage = LOADADDR(.data) + SIZEOF(.data); + +/* EOF */ diff --git a/src/kernel_patches/linux-2.4.2-SiS.patch b/src/kernel_patches/linux-2.4.2-SiS.patch new file mode 100644 index 0000000000..268a334ef6 --- /dev/null +++ b/src/kernel_patches/linux-2.4.2-SiS.patch @@ -0,0 +1,2712 @@ +diff -urN linux-2.4.2-official/arch/i386/Linuxbios.in linux-2.4.2-linuxbios/arch/i386/Linuxbios.in +--- linux-2.4.2-official/arch/i386/Linuxbios.in Thu Jan 1 08:00:00 1970 ++++ linux-2.4.2-linuxbios/arch/i386/Linuxbios.in Tue Feb 27 15:58:07 2001 +@@ -0,0 +1,7 @@ ++mainmenu_option next_comment ++comment 'Linuxbios Options' ++bool 'Force IDE Controllers on?' CONFIG_LINUXBIOS_FORCE_IDE_CONTROLLER_ON ++bool 'Wait for HDA to spin up?' CONFIG_LINUXBIOS_WAIT_HDA_SPINUP ++bool 'Do not touch debug registers?' CONFIG_LINUXBIOS_DONT_TOUCH_DR ++bool 'LOBOS (Linux Os Boots OS)?' CONFIG_LINUXBIOS_LOBOS ++endmenu +diff -urN linux-2.4.2-official/arch/i386/config.in linux-2.4.2-linuxbios/arch/i386/config.in +--- linux-2.4.2-official/arch/i386/config.in Tue Jan 9 05:27:56 2001 ++++ linux-2.4.2-linuxbios/arch/i386/config.in Tue Feb 27 15:58:07 2001 +@@ -367,3 +367,13 @@ + #bool 'Debug kmalloc/kfree' CONFIG_DEBUG_MALLOC + bool 'Magic SysRq key' CONFIG_MAGIC_SYSRQ + endmenu ++ ++mainmenu_option next_comment ++comment 'LinuxBIOS' ++ ++tristate 'LinuxBIOS Support' CONFIG_LINUXBIOS ++if [ "$CONFIG_LINUXBIOS" != "n" ]; then ++ source arch/i386/Linuxbios.in ++fi ++ ++endmenu +diff -urN linux-2.4.2-official/arch/i386/kernel/process.c linux-2.4.2-linuxbios/arch/i386/kernel/process.c +--- linux-2.4.2-official/arch/i386/kernel/process.c Sat Feb 10 03:29:44 2001 ++++ linux-2.4.2-linuxbios/arch/i386/kernel/process.c Tue Feb 27 15:58:08 2001 +@@ -49,6 +49,131 @@ + + #include + ++#define CONFIG_LINUXBIOS_PM ++#ifdef CONFIG_LINUXBIOS_PM ++#include ++void ++sis503_reset(struct pci_dev *dev) ++{ ++ unsigned char b; ++ unsigned short acpi_base; ++ ++ printk(KERN_ERR __FUNCTION__ ": starting reset operation. \n"); ++ ++ /* Enable ACPI by set B7 on Reg 0x40, LPC */ ++ pci_read_config_byte(dev, 0x40, &b); ++ pci_write_config_byte(dev, 0x40, b | 0x80); ++ printk(KERN_ERR __FUNCTION__ ": enabled ACPI. \n"); ++ ++ /* get the ACPI base address for register 0x74,0x75 of LPC */ ++ pci_read_config_word(dev, 0x74, &acpi_base); ++ printk(KERN_ERR __FUNCTION__ ":acpi base: %x\n", acpi_base); ++ ++ /* Set software watchdog timer init value */ ++ outb(0x03, 0x4a + acpi_base); ++ printk(KERN_ERR __FUNCTION__ ": set the dog. \n"); ++ ++ printk(KERN_ERR __FUNCTION__ ": enabling dog. \n"); ++ /* Software watchdog enable, issue PCIRST# when time expire */ ++ outb(0x8f, 0x4b + acpi_base); ++ ++ printk(KERN_ERR __FUNCTION__ ": We should reset soon. \n"); ++} ++ ++void ++sis503_off(struct pci_dev *dev) ++{ ++ unsigned char b; ++ unsigned short acpi_base; ++ ++ printk(KERN_ERR __FUNCTION__ ": starting reset operation. \n"); ++ /* Enable ACPI by set B7 on Reg 0x40, LPC */ ++ pci_read_config_byte(dev, 0x40, &b); ++ pci_write_config_byte(dev, 0x40, b | 0x80); ++ printk(KERN_ERR __FUNCTION__ ": enabled ACPI. \n"); ++ ++ /* get the ACPI base address for register 0x74,0x75 of LPC */ ++ pci_read_config_word(dev, 0x74, &acpi_base); ++ printk (KERN_ERR __FUNCTION__ ":acpi base: %x\n", acpi_base); ++ ++ /* ACPI Register 5, Bit 10-12, Sleeping Type, ++ set to 101 -> S5, soft_off */ ++ outb(0x14, 0x05 + acpi_base); ++ printk(KERN_ERR __FUNCTION__ ": DONE setting sleep type. \n"); ++ ++ /* ACPI Register 5, Bit 13, Sleep Enable */ ++ outb(0x20 | 0x14, 0x05 + acpi_base); ++ printk(KERN_ERR __FUNCTION__ ": DONE sleep enable. \n"); ++} ++ ++struct pci_dev * pci_find_device(unsigned int vendor, unsigned int device, ++ const struct pci_dev *from); ++ ++struct linuxbios_control { ++ u_short vendor, device; ++ void (*poweroff)(struct pci_dev *); ++ void (*reset)(struct pci_dev *); ++}; ++ ++struct linuxbios_control controls[] = { ++ {PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, sis503_off, sis503_reset} ++}; ++ ++struct linuxbios_control *findcontrol(struct pci_dev **d) ++{ ++ struct linuxbios_control *lb = controls, *retval = 0; ++ int i; ++ ++ printk(KERN_ERR __FUNCTION__ ": Find vendor 0x%x device 0x%x\n", ++ lb->vendor, lb->device); ++ for(lb = controls, i = 0; ++ (i < sizeof(controls)/sizeof(controls[0])) && (! retval); ++ i++, lb++) ++ { ++ *d = pci_find_device(lb->vendor, lb->device, 0); ++ if (*d) ++ retval = lb; ++ } ++ ++ printk(KERN_ERR __FUNCTION__ ": result of find is %p\n", retval); ++ return retval; ++} ++ ++void ++linuxbios_poweroff(void) ++{ ++ struct linuxbios_control *lb = 0; ++ struct pci_dev *dev; ++ ++ printk(KERN_ERR __FUNCTION__ ": find an lb\n"); ++ lb = findcontrol(&dev); ++ ++ printk(KERN_ERR __FUNCTION__ ": found lb %p, call %p\n", ++ lb, lb ? lb->poweroff : 0); ++ if (lb && (lb->poweroff)) ++ lb->poweroff(dev); ++ printk(KERN_ERR __FUNCTION__ ": Returning? Can't happen, I thought?\n"); ++} ++ ++void ++linuxbios_reset(void) ++{ ++ struct linuxbios_control *lb = 0; ++ struct pci_dev *dev; ++ ++ printk(KERN_ERR __FUNCTION__ ": find an lb\n"); ++ lb = findcontrol(&dev); ++ ++ printk(KERN_ERR __FUNCTION__ ": found lb %p, call %p\n", ++ lb, lb ? lb->reset : 0); ++ if (lb && (lb->reset)) ++ lb->reset(dev); ++ printk(KERN_ERR __FUNCTION__ ": Returning? Can't happen, I thought?\n"); ++} ++ ++#endif ++ ++ + asmlinkage void ret_from_fork(void) __asm__("ret_from_fork"); + + int hlt_counter; +@@ -353,6 +478,9 @@ + smp_send_stop(); + disable_IO_APIC(); + #endif ++#ifdef CONFIG_LINUXBIOS_PM ++ linuxbios_reset(); ++#endif + + if(!reboot_thru_bios) { + /* rebooting needs to touch the page at absolute addr 0 */ +@@ -380,6 +508,11 @@ + + void machine_power_off(void) + { ++ printk("MACHINE_POWER_OFF\n"); ++#ifdef CONFIG_LINUXBIOS_PM ++ linuxbios_poweroff(); ++#endif ++ + if (pm_power_off) + pm_power_off(); + } +diff -urN linux-2.4.2-official/drivers/ide/ide-pci.c linux-2.4.2-linuxbios/drivers/ide/ide-pci.c +--- linux-2.4.2-official/drivers/ide/ide-pci.c Wed Jan 3 08:58:45 2001 ++++ linux-2.4.2-linuxbios/drivers/ide/ide-pci.c Tue Feb 27 15:58:08 2001 +@@ -603,8 +603,19 @@ + for (port = 0; port <= 1; ++port) { + unsigned long base = 0, ctl = 0; + ide_pci_enablebit_t *e = &(d->enablebits[port]); ++#ifndef CONFIG_LINUXBIOS_FORCE_IDE_CONTROLLER_ON + if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) || (tmp & e->mask) != e->val)) + continue; /* port not enabled */ ++#else ++ /* force 'em on! */ ++ if (e->reg) { ++ pci_read_config_byte(dev, e->reg, &tmp); ++ tmp |= e->val; ++ pci_write_config_byte(dev, e->reg, tmp); ++ printk("%s: LINUXBIOS, so Jammed the enable on!\n", ++ d->name); ++ } ++#endif + if (IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT366) && (port) && (class_rev < 0x03)) + return; + if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE || (dev->class & (port ? 4 : 1)) != 0) { +diff -urN linux-2.4.2-official/drivers/ide/ide-probe.c linux-2.4.2-linuxbios/drivers/ide/ide-probe.c +--- linux-2.4.2-official/drivers/ide/ide-probe.c Sat Feb 10 03:30:23 2001 ++++ linux-2.4.2-linuxbios/drivers/ide/ide-probe.c Tue Feb 27 15:58:08 2001 +@@ -308,6 +308,13 @@ + if ((drive->media != ide_disk) && (cmd == WIN_IDENTIFY)) + return 4; + } ++#ifdef CONFIG_LINUXBIOS_WAIT_HDA_SPINUP ++ if (! strncmp(drive->name, "hda", 3)) { ++ printk("jamming drive present for %s\n", drive->name); ++ drive->present = 1; ++ } ++#endif ++ + #ifdef DEBUG + printk("probing for %s: present=%d, media=%d, probetype=%s\n", + drive->name, drive->present, drive->media, +diff -urN linux-2.4.2-official/drivers/mtd/docprobe.c linux-2.4.2-linuxbios/drivers/mtd/docprobe.c +--- linux-2.4.2-official/drivers/mtd/docprobe.c Wed Feb 28 09:29:04 2001 ++++ linux-2.4.2-linuxbios/drivers/mtd/docprobe.c Tue Feb 27 15:58:08 2001 +@@ -39,7 +39,7 @@ + a Millennium enough that they go through and work out what the + difference is :) + */ +-#define DOC_SINGLE_DRIVER ++#undef DOC_SINGLE_DRIVER + + #include + #include +diff -urN linux-2.4.2-official/drivers/video/sis/Makefile linux-2.4.2-linuxbios/drivers/video/sis/Makefile +--- linux-2.4.2-official/drivers/video/sis/Makefile Sat Dec 30 06:07:23 2000 ++++ linux-2.4.2-linuxbios/drivers/video/sis/Makefile Thu Feb 15 07:58:16 2001 +@@ -4,9 +4,7 @@ + + O_TARGET := sisfb.o + +-obj-y := sis_main.o sis_300.o sis_301.o ++obj-y := sisfb_lite.o + obj-m := $(O_TARGET) + +-include $(TOPDIR)/Rules.make +- +- ++include $(TOPDIR)/Rules.make +\ No newline at end of file +diff -urN linux-2.4.2-official/drivers/video/sis/sisfb_lite.c linux-2.4.2-linuxbios/drivers/video/sis/sisfb_lite.c +--- linux-2.4.2-official/drivers/video/sis/sisfb_lite.c Thu Jan 1 08:00:00 1970 ++++ linux-2.4.2-linuxbios/drivers/video/sis/sisfb_lite.c Tue Feb 27 10:38:59 2001 +@@ -0,0 +1,2313 @@ ++/* sisfb_lite.c: SiSFB Lite, Frame Buffer Device Driver for SiS 540/630/730 requires no VGA BIOS ++ * ++ * Copyright 2000 Ollie Lho ++ * ++ * This driver is derived form an eraly version of sisfb.c which is: ++ * This driver is partly based on the VBE 2.0 compliant graphic ++ * boards framebuffer driver, which is ++ * ++ * (c) 1998 Gerd Knorr ++ * ++ * This driver is implemented by the Author for his own personal interests and is NOT a ++ * commitment NOR supported officially by Silicon Integrated System Corp. Please direct ++ * any bug report/question to the Author and don't bother SiS Technical Support Personell. ++ * ++ * ++ * Reference: ++ * 1. SiS 6326 AGP/PCI Graphics & Video Acclerator. Rev 1.0, May 12, 1997 ++ * 2. Programmer's Guide to the EGA,VGA, and Super VGA Card. Thrid Edition, ++ * Richard F. Ferraro, Addison-Welsey, Aug. 1994 ++ * 3. Glamour Design Guideline V0.8 ++ * 4. Graphics Hardware by Geert Uytterhoeven ++ * 5. sis86c201.c in XFree86 3.3.6 ++ * ++ * ToDo: ++ * 0. more document ++ * 1. figure out if we need both default_par and current_par ++ * 2. make sure we have to set_var when init or NOT !!! ++ * 4. MMAP ++ * 5. 2D Acceleration ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include