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UPSTREAM: MAINTAINERS/RISCV: Cover mb/emulation/spike-riscv
BUG=None BRANCH=None TEST=None Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16988 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Change-Id: Id5f3f7f25041189d137ef4daa9f63a3b478763bc Reviewed-on: https://chromium-review.googlesource.com/400108 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -124,7 +124,7 @@ M: Ronald Minnich <rminnich@gmail.com>
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S: Maintained
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F: src/arch/riscv/
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F: src/soc/ucb/
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F: src/mainboard/emulation/qemu-riscv/
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F: src/mainboard/emulation/*-riscv/
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POWER8 ARCHITECTURE
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M: Ronald Minnich <rminnich@gmail.com>
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