From b68f1ac97951efe1164348880ca5bd7a5ac4c6e4 Mon Sep 17 00:00:00 2001 From: Ward Vandewege Date: Thu, 17 Apr 2008 17:27:13 +0000 Subject: [PATCH] Add pcengines alix.2c3 support. There is still one outstanding issue - eth2 and the USB ports fight over IRQs. Signed-off-by: Ward Vandewege Acked-by: Marc Jones git-svn-id: svn://coreboot.org/repository/coreboot-v3@663 f3766cd6-281f-0410-b1cd-43a5c92072e9 --- mainboard/pcengines/Kconfig | 12 ++ mainboard/pcengines/alix2c3/Kconfig | 28 ++++ mainboard/pcengines/alix2c3/Makefile | 33 +++++ mainboard/pcengines/alix2c3/cmos.layout | 75 +++++++++++ mainboard/pcengines/alix2c3/defconfig | 96 +++++++++++++ mainboard/pcengines/alix2c3/dts | 54 ++++++++ mainboard/pcengines/alix2c3/initram.c | 165 +++++++++++++++++++++++ mainboard/pcengines/alix2c3/irq_tables.h | 109 +++++++++++++++ mainboard/pcengines/alix2c3/stage1.c | 52 +++++++ 9 files changed, 624 insertions(+) create mode 100644 mainboard/pcengines/alix2c3/Kconfig create mode 100644 mainboard/pcengines/alix2c3/Makefile create mode 100644 mainboard/pcengines/alix2c3/cmos.layout create mode 100644 mainboard/pcengines/alix2c3/defconfig create mode 100644 mainboard/pcengines/alix2c3/dts create mode 100644 mainboard/pcengines/alix2c3/initram.c create mode 100644 mainboard/pcengines/alix2c3/irq_tables.h create mode 100644 mainboard/pcengines/alix2c3/stage1.c diff --git a/mainboard/pcengines/Kconfig b/mainboard/pcengines/Kconfig index a17bde991a..d096baf281 100644 --- a/mainboard/pcengines/Kconfig +++ b/mainboard/pcengines/Kconfig @@ -35,7 +35,19 @@ config BOARD_PCENGINES_ALIX1C help PC Engines ALIX1.C. +config BOARD_PCENGINES_ALIX2C3 + bool "ALIX.2C3" + select ARCH_X86 + select CPU_AMD_GEODELX + select OPTION_TABLE + select NORTHBRIDGE_AMD_GEODELX + select SOUTHBRIDGE_AMD_CS5536 + select PIRQ_TABLE + help + PC Engines ALIX.2C3. + endchoice source "mainboard/pcengines/alix1c/Kconfig" +source "mainboard/pcengines/alix2c3/Kconfig" diff --git a/mainboard/pcengines/alix2c3/Kconfig b/mainboard/pcengines/alix2c3/Kconfig new file mode 100644 index 0000000000..0a12dbb0d9 --- /dev/null +++ b/mainboard/pcengines/alix2c3/Kconfig @@ -0,0 +1,28 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 coresystems GmbH +## (Written by Stefan Reinauer for coresystems GmbH) +## Copyright (C) 2007 Ronald G. Minnich +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config MAINBOARD_NAME + string + default pcengines/alix2c3 + depends BOARD_PCENGINES_ALIX2C3 + help + This is the default mainboard name. diff --git a/mainboard/pcengines/alix2c3/Makefile b/mainboard/pcengines/alix2c3/Makefile new file mode 100644 index 0000000000..da4c25a6c6 --- /dev/null +++ b/mainboard/pcengines/alix2c3/Makefile @@ -0,0 +1,33 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2006-2007 coresystems GmbH +## (Written by Stefan Reinauer for coresystems GmbH) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o + +INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ + $(src)/northbridge/amd/geodelx/raminit.c \ + $(src)/arch/x86/geodelx/geodelx.c + +STAGE2_MAINBOARD_OBJ = + +$(obj)/coreboot.vpd: + $(Q)printf " BUILD DUMMY VPD\n" + $(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT) + diff --git a/mainboard/pcengines/alix2c3/cmos.layout b/mainboard/pcengines/alix2c3/cmos.layout new file mode 100644 index 0000000000..7b3fe21b49 --- /dev/null +++ b/mainboard/pcengines/alix2c3/cmos.layout @@ -0,0 +1,75 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 1 e 0 dcon_present +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 1007 1008 + + diff --git a/mainboard/pcengines/alix2c3/defconfig b/mainboard/pcengines/alix2c3/defconfig new file mode 100644 index 0000000000..32144bb0f8 --- /dev/null +++ b/mainboard/pcengines/alix2c3/defconfig @@ -0,0 +1,96 @@ +# +# Automatically generated make config: don't edit +# coreboot version: 3.0."656"' +# Wed Apr 9 20:59:03 2008 +# + +# +# General setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_EXPERT is not set +CONFIG_LOCALVERSION="" + +# +# Mainboard +# +# CONFIG_VENDOR_ADL is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_EMULATION is not set +CONFIG_VENDOR_PCENGINES=y +CONFIG_MAINBOARD_NAME="pcengines/alix2c3" +# CONFIG_BOARD_PCENGINES_ALIX1C is not set +CONFIG_BOARD_PCENGINES_ALIX2C3=y +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +CONFIG_COREBOOT_ROMSIZE_KB_512=y +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +CONFIG_COREBOOT_ROMSIZE_KB=512 +CONFIG_ARCH_X86=y +CONFIG_ARCH="x86" +CONFIG_CPU_AMD_GEODELX=y +CONFIG_OPTION_TABLE=y +CONFIG_PIRQ_TABLE=y +CONFIG_CARBASE=0x80000 +CONFIG_CARSIZE=0x8000 + +# +# Compression +# +CONFIG_COMPRESSION_LZMA=y +# CONFIG_COMPRESSION_NRV2B is not set +CONFIG_DEFAULT_COMPRESSION_LZMA=y +# CONFIG_DEFAULT_COMPRESSION_NRV2B is not set +# CONFIG_DEFAULT_COMPRESSION_NONE is not set + +# +# Console +# +CONFIG_CONSOLE=y +CONFIG_CONSOLE_LOGLEVEL_8=y +# CONFIG_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_CONSOLE_LOGLEVEL_0 is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +CONFIG_CONSOLE_SERIAL=y +CONFIG_CONSOLE_SERIAL_COM1=y +# CONFIG_CONSOLE_SERIAL_COM2 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_CONSOLE_BUFFER=y + +# +# Devices +# +CONFIG_PCI_OPTION_ROM_RUN=y +# CONFIG_PCI_OPTION_ROM_RUN_X86EMU is not set +CONFIG_PCI_OPTION_ROM_RUN_VM86=y +# CONFIG_PCI_OPTION_ROM_RUN_NONE is not set +# CONFIG_MULTIPLE_VGA_INIT is not set +# CONFIG_INITIALIZE_ONBOARD_VGA_FIRST is not set + +# +# Power management +# +CONFIG_NORTHBRIDGE_AMD_GEODELX=y +CONFIG_SOUTHBRIDGE_AMD_CS5536=y +CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION_RAMSIZE=32 + +# +# Payload +# +# CONFIG_PAYLOAD_ELF_LOADER is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_FILE="../payload.elf" +# CONFIG_ZERO_AFTER_PAYLOAD is not set diff --git a/mainboard/pcengines/alix2c3/dts b/mainboard/pcengines/alix2c3/dts new file mode 100644 index 0000000000..1a1be04653 --- /dev/null +++ b/mainboard/pcengines/alix2c3/dts @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/{ + mainboard-vendor = "PC Engines"; + mainboard-name = "ALIX.2C3"; + cpus { }; + apic@0 { + /config/("northbridge/amd/geodelx/apic"); + }; + domain@0 { + /config/("northbridge/amd/geodelx/domain"); + pci@1,0 { + /config/("northbridge/amd/geodelx/pci"); + }; + pci@15,0 { + /config/("southbridge/amd/cs5536/dts"); + enable_ide = "1"; + /* Interrupt enables for LPC bus. + * Each bit is an IRQ 0-15. */ + lpc_serirq_enable = "0x000010da"; + /* LPC IRQ polarity. Each bit is an IRQ 0-15. */ + lpc_serirq_polarity = "0x0000EF25"; + /* 0:continuous 1:quiet */ + lpc_serirq_mode = "1"; + /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. + * See virtual PIC spec. */ + enable_gpio_int_route = "0x0D0C0700"; + /* COM1 settings */ + com1_enable = "1"; + com1_address = "0x3f8"; + com1_irq = "4"; + /* this board does not really have vga; disable it (pci device 00:01.1) */ + unwanted_vpci = < 80000900 0 >; + }; + }; +}; diff --git a/mainboard/pcengines/alix2c3/initram.c b/mainboard/pcengines/alix2c3/initram.c new file mode 100644 index 0000000000..fc1cbfa219 --- /dev/null +++ b/mainboard/pcengines/alix2c3/initram.c @@ -0,0 +1,165 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define _MAINOBJECT + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MANUALCONF 0 /* Do automatic strapped PLL config */ +#define PLLMSRHI 0x00001490 /* manual settings for the PLL */ +#define PLLMSRLO 0x02000030 +#define DIMM0 ((u8) 0xA0) +#define DIMM1 ((u8) 0xA2) + +/* The part is a Hynix hy5du121622ctp-d43. + * + * HY 5D U 12 16 2 2 C T P D43 + * Hynix + * DDR SDRAM (5D) + * VDD 2.5 VDDQ 2.5 (U) + * 512M 8K REFRESH (12) + * x16 (16) + * 4banks (2) + * SSTL_2 (2) + * 4th GEN die (C) + * Normal Power Consumption ( ) + * TSOP (T) + * Single Die () + * Lead Free (P) + * DDR400 3-3-3 (D43) + */ + +struct spd_entry { + u8 address; + u8 data; +}; + +/* Save space by using a short list of SPD values used by Geode LX Memory init */ +static const struct spd_entry spd_table[] = { + {SPD_ACCEPTABLE_CAS_LATENCIES, 0x10}, + {SPD_BANK_DENSITY, 0x40}, + {SPD_DEVICE_ATTRIBUTES_GENERAL, 0xff}, + {SPD_MEMORY_TYPE, 7}, + {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 10}, /* A guess for the tRAC value */ + {SPD_MODULE_ATTRIBUTES, 0xff}, /* FIXME later when we figure out. */ + {SPD_NUM_BANKS_PER_SDRAM, 4}, + {SPD_PRIMARY_SDRAM_WIDTH, 8}, + {SPD_NUM_DIMM_BANKS, 1}, /* ALIX.2C3 is 1 bank. */ + {SPD_NUM_COLUMNS, 0xa}, + {SPD_NUM_ROWS, 3}, + {SPD_REFRESH, 0x3a}, + {SPD_SDRAM_CYCLE_TIME_2ND, 60}, + {SPD_SDRAM_CYCLE_TIME_3RD, 75}, + {SPD_tRAS, 40}, + {SPD_tRCD, 15}, + {SPD_tRFC, 70}, + {SPD_tRP, 15}, + {SPD_tRRD, 10}, +}; + +/** + * Given an SMBUS device, and an address in that device, return the value of SPD + * for that device. In this mainboard, the only one that can return is DIMM0. + * @param device The device number + * @param address The address in SPD rom to return the value of + * @returns The value + */ +u8 spd_read_byte(u16 device, u8 address) +{ + int i; + /* returns 0xFF on any failures */ + u8 ret = 0xff; + + printk(BIOS_DEBUG, "spd_read_byte dev %04x", device); + if (device == DIMM0) { + for (i = 0; i < ARRAY_SIZE(spd_table); i++) { + if (spd_table[i].address == address) { + ret = spd_table[i].data; + break; + } + } + if (i == ARRAY_SIZE(spd_table)) + printk(BIOS_DEBUG, " addr %02x does not exist in SPD table", + address); + } + + printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, ret); + return ret; +} + +/** + * Placeholder in case we ever need it. Since this file is a + * template for other motherboards, we want this here and we want the + * call in the right place. + */ + +static void mb_gpio_init(void) +{ + /* Early mainboard specific GPIO setup */ +} + +/** + * main for initram for the PC Engines Alix.2c3. It might seem that you + * could somehow do these functions in, e.g., the cpu code, but the + * order of operations and what those operations are is VERY strongly + * mainboard dependent. It's best to leave it in the mainboard code. + */ +int main(void) +{ + printk(BIOS_DEBUG, "Hi there from stage1\n"); + post_code(POST_START_OF_MAIN); + + system_preinit(); + printk(BIOS_DEBUG, "done preinit\n"); + + mb_gpio_init(); + printk(BIOS_DEBUG, "done gpio init\n"); + + pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO); + printk(BIOS_DEBUG, "done pll reset\n"); + + cpu_reg_init(0, DIMM0, DIMM1); + printk(BIOS_DEBUG, "done cpu reg init\n"); + + sdram_set_registers(); + printk(BIOS_DEBUG, "done sdram set registers\n"); + + sdram_set_spd_registers(DIMM0, DIMM1); + printk(BIOS_DEBUG, "done sdram set spd registers\n"); + + sdram_enable(DIMM0, DIMM1); + printk(BIOS_DEBUG, "done sdram enable\n"); + + /* Check low memory */ + /*ram_check(0x00000000, 640*1024); */ + + printk(BIOS_DEBUG, "stage1 returns\n"); + return 0; +} diff --git a/mainboard/pcengines/alix2c3/irq_tables.h b/mainboard/pcengines/alix2c3/irq_tables.h new file mode 100644 index 0000000000..ed7fb436a5 --- /dev/null +++ b/mainboard/pcengines/alix2c3/irq_tables.h @@ -0,0 +1,109 @@ +/* +* This file is part of the coreboot project. +* +* Copyright (C) 2007 Advanced Micro Devices, Inc. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include + +/* Number of slots and devices in the PIR table */ +#define IRQ_SLOT_COUNT 6 + +/* Platform IRQs */ +#define PIRQA 9 +#define PIRQB 10 +#define PIRQC 11 +#define PIRQD 12 + +/* Map */ +#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ +#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ +#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ +#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ + +/* Link */ +#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ +#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ +#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ +#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ + +/* + * ALIX.2C3 interrupt wiring. + * + * Devices are: + * + * 00:01.0 Host bridge: Advanced Micro Devices [AMD] Unknown device 2080 (rev 31) + * 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX AES Security Block + * 00:09.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) + * 00:0a.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) + * 00:0b.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) + * 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03) + * 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01) + * 00:0f.3 Multimedia audio controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio (rev 01) + * 00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02) + * 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02) + * + * The only devices that interrupt are: + + * What Device IRQ PIN PIN WIRED TO + * ------------------------------------------------- + * AES 00:01.2 09 01 A A + * eth0 00:09.0 09 01 A B + * eth1 00:0a.0 10 01 A C + * eth2 00:0b.0 11 01 A D + * minipci 00:0c.0 09 01 A A + * audio 00:0f.3 05 02 B internal + * usb (ohci) 00:0f.4 15 04 D internal + * usb (ehci) 00:0f.5 15 04 D internal + * + */ + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, + PIRQ_VERSION, + 32 + 16 * IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ + 0x00, /* IRQs devoted exclusively to PCI usage */ + 0x100B, /* Vendor */ + 0x002B, /* Device */ + 0, /* Crap (miniport) */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ + 0x00, /* Checksum */ + { + /* If you change the number of entries, change IRQ_SLOT_COUNT above! */ + + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + + /* CPU */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, + + /* On-board eth0 */ + {0x00, (0x09 << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, + + /* On-board eth1 */ + {0x00, (0x0A << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, + + /* On-board eth2 */ + {0x00, (0x0B << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, + + /* Mini PCI (slot 1) */ + {0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0}, + + /* Chipset slots */ + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, + } +}; diff --git a/mainboard/pcengines/alix2c3/stage1.c b/mainboard/pcengines/alix2c3/stage1.c new file mode 100644 index 0000000000..c971b524eb --- /dev/null +++ b/mainboard/pcengines/alix2c3/stage1.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SERIAL_IOBASE 0x3f8 + +void hardware_stage1(void) +{ + post_code(POST_START_OF_MAIN); + geodelx_msr_init(); + + cs5536_stage1(); + + /* NOTE: must do this AFTER the early_setup! + * it is counting on some early MSR setup + * for cs5536. + */ + cs5536_setup_onchipuart(1); +} + +void mainboard_pre_payload(void) +{ + geode_pre_payload(); + banner(BIOS_DEBUG, "mainboard_pre_payload: done"); +}