diff --git a/src/arch/alpha/config/make.base b/src/arch/alpha/config/make.base index 7ed399a9bf..1c733dbf9f 100644 --- a/src/arch/alpha/config/make.base +++ b/src/arch/alpha/config/make.base @@ -1,42 +1,19 @@ biosbase 0 rambase 0x8000 -makedefine CC:=gcc -makedefine LIBGCC_FILE_NAME := $(shell $(CC) -print-libgcc-file-name) -makedefine GCC_INC_DIR := $(shell $(CC) -print-search-dirs | sed -ne "s/install: \(.*\)/\1include/gp") -makedefine CPPFLAGS= -I$(TOP)/src/include -I$(TOP)/src/arch/$(ARCH)/include -I$(GCC_INC_DIR) $(CPUFLAGS) -makedefine CFLAGS= $(CPU_OPT) $(CPPFLAGS) -O2 -nostdinc -nostdlib -fno-builtin -Wall + +option USE_DEFAULT_LAYOUT=1 +ldscript arch/alpha/config/ldscript.base USE_DEFAULT_LAYOUT + makedefine LINK = ld -T ldscript.ld -o $@ crt0.o linuxbios.a makerule all : linuxbios.rom ; makerule linuxbios.rom: linuxbios.strip makerom ; ./makerom -l0x310000 -i7 -v linuxbios.strip -o linuxbios.rom -makerule linuxbios.strip: linuxbios ; objcopy -O binary -R .note -R .comment -S linuxbios linuxbios.strip -makerule linuxbios: linuxbios.a ; @rm -f biosobject -makerule etags: $(SOURCES) ; etags $(SOURCES) -makerule tags: $(SOURCES) ; ctags $(SOURCES) -makerule documentation: $(SOURCES) ; doxygen LinuxBIOSDoc.config -addaction linuxbios $(LINK) -addaction linuxbios nm -n linuxbios > linuxbios.map -makerule ldscript.ld : ldscript.options $(LDSUBSCRIPTS-1) ; echo "INCLUDE ldscript.options" > ldscript.ld ; for file in $(LDSUBSCRIPTS-1) ; do echo "INCLUDE $$file" >> ldscript.ld ; done -makerule linuxbios.a : $(OBJECTS-1) ; rm -f linuxbios.a -addaction linuxbios.a ar cr linuxbios.a $(OBJECTS-1) - -makerule crt0.s: crt0.S ; $(CC) $(CPPFLAGS) -I$(TOP)/src -E $< > crt0.s - -makerule crt0.o : crt0.s; $(CC) $(CPU_OPT) -c crt0.s #makerule makerom: $(TOP)/util/makerom/makerom.c $(TOP)/util/makerom/compress.c ; $(CC) -o makerom $(TOP)/util/makerom/makerom.c $(TOP)/util/makerom/compress.c -makerule clean : ; rm -f linuxbios.* *.o mkrom xa? *~ -addaction clean rm -f linuxbios crt0.s -addaction clean rm -f a.out *.s *.l -addaction clean rm -f TAGS tags -addaction clean rm -f docipl - +addaction clean rm -f makerom # do standard config files that the user need not specify # for now, this is just 'lib', but it may be more later. dir /src/arch/alpha -dir /src/lib -dir /src/boot -dir /src/rom dir /util/makerom diff --git a/src/arch/i386/config/crt0.base b/src/arch/i386/config/crt0.base index f37b08684b..ed569449bc 100644 --- a/src/arch/i386/config/crt0.base +++ b/src/arch/i386/config/crt0.base @@ -26,9 +26,9 @@ CRT0_PARAMETERS -#if defined(SERIAL_CONSOLE) && defined(DEBUG) +#if defined(SERIAL_CONSOLE) && (DEFAULT_CONSOLE_LOGLEVEL >= 7) TTYS0_TX_STRING($str_after_ram) -#endif /* defined(SERIAL_CONSOLE) && defined(DEBUG) */ +#endif /* clear boot_complete flag */ xorl %ebp, %ebp @@ -96,10 +96,9 @@ __main: */ intel_chip_post_macro(0xfe) /* post fe */ -#if defined(SERIAL_CONSOLE) && defined(DEBUG) +#if defined(SERIAL_CONSOLE) && (DEFAULT_CONSOLE_LOGLEVEL >= 7) TTYS0_TX_STRING($str_pre_main) -#endif /* defined(SERIAL_CONSOLE) && defined(DEBUG) */ - +#endif /* memory is up. Let\'s do the rest in C -- much easier. */ diff --git a/src/arch/i386/config/make.base b/src/arch/i386/config/make.base index 1d512d8b49..32da43f8f5 100644 --- a/src/arch/i386/config/make.base +++ b/src/arch/i386/config/make.base @@ -6,63 +6,43 @@ option ROM_IMAGE_SIZE=65536 option MAX_CPUS=1 # Reserve 256K for the heap option HEAP_SIZE=0x40000 -# Reserve 64K for each stack -option STACK_SIZE=0x10000 +# Reserve 8K for each stack +option STACK_SIZE=0x2000 # By default on x86 we have a memory hole between 640K and 1MB option MEMORY_HOLE=1 -makedefine CC:=gcc -makedefine CPP:= gcc -x assembler-with-cpp -DASSEMBLY -E -makedefine LIBGCC_FILE_NAME := $(shell $(CC) -print-libgcc-file-name) -makedefine GCC_INC_DIR := $(shell $(CC) -print-search-dirs | sed -ne "s/install: \(.*\)/\1include/gp") -makedefine CPPFLAGS := -I$(TOP)/src/include -I$(TOP)/src/arch/$(ARCH)/include -I$(GCC_INC_DIR) $(CPUFLAGS) -makedefine CFLAGS := $(CPU_OPT) $(CPPFLAGS) -O2 -nostdinc -nostdlib -fno-builtin -Wall +option USE_DEFAULT_LAYOUT=1 +ldscript arch/i386/config/ldscript.base USE_DEFAULT_LAYOUT +ldscript arch/i386/config/ldscript.cacheram USE_CACHE_RAM + +# How do I add -mprefered-stack-boundary=2 if the compiler supports it? +# On x86 tt results in a code size reduction. +# + +dir /src/config + makerule all : romimage ; makerule floppy : all ; mcopy -o romimage a: makerule romimage : linuxbios.rom vmlinux.bin.gz.block ; cat vmlinux.bin.gz.block linuxbios.rom > romimage + makerule linuxbios.rom: linuxbios.strip ; addaction linuxbios.rom export size=`ls -l linuxbios.strip | (read p c u g size r ; echo $$size)` ; \ addaction linuxbios.rom echo $$size ; \ addaction linuxbios.rom dd if=linuxbios.strip of=linuxbios.rom bs=1 seek=`expr $(ROM_IMAGE_SIZE) - $$size` -makerule linuxbios.strip: linuxbios ; objcopy -O binary linuxbios linuxbios.strip -makerule linuxbios.o : crt0.o linuxbios.a $(LIBGCC_FILE_NAME) ; $(CC) -nostdlib -r -o $@ crt0.o linuxbios.a $(LIBGCC_FILE_NAME) - -makerule ldscript.ld : ldoptions $(LDSUBSCRIPTS-1) ; echo "INCLUDE ldoptions" > ldscript.ld ; for file in $(LDSUBSCRIPTS-1) ; do echo "INCLUDE $$file" >> ldscript.ld ; done - -makerule linuxbios: linuxbios.o ldscript.ld ; $(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld linuxbios.o -addaction linuxbios nm -n linuxbios > linuxbios.map - -makerule etags: $(SOURCES) ; etags $(SOURCES) -makerule tags: $(SOURCES) ; ctags $(SOURCES) -makerule documentation: $(SOURCES) ; doxygen LinuxBIOSDoc.config - -makerule linuxbios.a : $(OBJECTS-1) ; rm -f linuxbios.a -addaction linuxbios.a ar cr linuxbios.a $(OBJECTS-1) - -makerule crt0.s: crt0.S ; $(CPP) $(CPPFLAGS) -I$(TOP)/src $< > crt0.s - -makerule crt0.o : crt0.s; $(CC) $(CPU_OPT) -c crt0.s makerule mkrom: $(TOP)/mkrom/mkrom.c ; $(CC) -o mkrom $< -makerule clean : ; rm -f linuxbios.* vmlinux.* *.o mkrom xa? *~ -addaction clean rm -f linuxbios romimage crt0.s -addaction clean rm -f a.out *.s *.l -addaction clean rm -f TAGS tags -addaction clean rm -f docipl - makerule vmlinux.bin.gz.block : vmlinux.bin.gz ; dd conv=sync bs=448k if=vmlinux.bin.gz of=vmlinux.bin.gz.block makerule vmlinux.bin.gz: vmlinux.bin ;gzip -f -3 vmlinux.bin makerule vmlinux.bin: $(LINUX)/vmlinux ; objcopy -O binary -R .note -R .comment -S $< vmlinux.bin +addaction clean rm -f romimage mkrom vmlinux.* + # do standard config files that the user need not specify # for now, this is just 'lib', but it may be more later. dir /src/arch/i386 -dir /src/lib -dir /src/boot -dir /src/rom diff --git a/src/arch/i386/lib/Config b/src/arch/i386/lib/Config index 7a8a030079..ae679822b9 100644 --- a/src/arch/i386/lib/Config +++ b/src/arch/i386/lib/Config @@ -1,4 +1,4 @@ object i386_subr.o object params.o object hardwaremain.o -object pirq_routing.o +object pirq_routing.o HAVE_PIRQ_TABLE diff --git a/src/arch/i386/lib/i386_subr.c b/src/arch/i386/lib/i386_subr.c index e24614933d..72222371f1 100644 --- a/src/arch/i386/lib/i386_subr.c +++ b/src/arch/i386/lib/i386_subr.c @@ -9,6 +9,10 @@ #include #include +#if defined(SMP) || defined(IOAPIC) +#define APIC 1 +#endif + void cache_on(unsigned long totalram) { post_code(0x60); @@ -45,7 +49,7 @@ void interrupts_on() * see the Intel mp1.4 spec, page A-3 */ -#if defined(SMP) +#if defined(APIC) /* Only Pentium Pro and later have those MSR stuff */ unsigned long low, high; @@ -81,7 +85,7 @@ void interrupts_on() | (APIC_LVT_REMOTE_IRR |APIC_SEND_PENDING | APIC_DELIVERY_MODE_NMI) ); -#else /* SMP */ +#else /* APIC */ #ifdef i686 /* Only Pentium Pro and later have those MSR stuff */ unsigned long low, high; @@ -92,7 +96,7 @@ void interrupts_on() low &= ~APIC_BASE_MSR_ENABLE; wrmsr(APIC_BASE_MSR, low, high); #endif /* i686 */ -#endif /* SMP */ +#endif /* APIC */ printk_info("done.\n"); post_code(0x9b); } diff --git a/src/arch/i386/lib/pirq_routing.c b/src/arch/i386/lib/pirq_routing.c index 513debda79..6c34d47072 100644 --- a/src/arch/i386/lib/pirq_routing.c +++ b/src/arch/i386/lib/pirq_routing.c @@ -1,4 +1,3 @@ -#ifdef HAVE_PIRQ_TABLE #include #include #include @@ -61,5 +60,3 @@ void copy_pirq_routing_table(void) memcpy((char *) RTABLE_DEST, &intel_irq_routing_table, intel_irq_routing_table.size); printk_info("done.\n"); } -#endif /* HAVE_PIRQ_TABLE */ - diff --git a/src/arch/i386/lib/set_memory_size_noop.inc b/src/arch/i386/lib/set_memory_size_noop.inc new file mode 100644 index 0000000000..5943245f1a --- /dev/null +++ b/src/arch/i386/lib/set_memory_size_noop.inc @@ -0,0 +1,6 @@ +jmp set_memory_size_out + +set_memory_size: + RETSP + +set_memory_size_out: diff --git a/src/arch/i386/smp/ioapic.c b/src/arch/i386/smp/ioapic.c index 32214c738a..02b5935c78 100644 --- a/src/arch/i386/smp/ioapic.c +++ b/src/arch/i386/smp/ioapic.c @@ -24,61 +24,6 @@ struct ioapicreg ioapicregvalues[] = { #define NMI (4 << 8) #define SMI (2 << 8) #define INT (1 << 8) -#if 0 /* L440GX */ - {0x00, DISABLED, NONE}, - {0x01, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x59, ALL}, - {0x02, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x51, ALL}, - {0x03, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x61, NONE}, - {0x04, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x69, ALL}, - {0x05, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x71, NONE}, - {0x06, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x79, NONE}, - {0x07, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x81, NONE}, - {0x08, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x89, ALL}, - {0x09, DISABLED, NONE}, - {0x0a, DISABLED, NONE}, - {0x0b, DISABLED, NONE}, - {0x0c, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x91, ALL}, - {0x0d, DISABLED, NONE}, - {0x0e, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x99, ALL}, - {0x0f, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0xa1, ALL}, - {0x10, DISABLED, NONE}, - {0x11, DISABLED, NONE}, - {0x12, DISABLED, NONE}, - {0x13, ENABLED|TRIGGER_LEVEL|POLARITY_LOW|LOGICAL_DEST|INT|0xa9, ALL}, - {0x14, DISABLED, NONE}, - {0x15, ENABLED|TRIGGER_LEVEL|POLARITY_LOW|LOGICAL_DEST|INT|0xb1, ALL}, - {0x16, DISABLED, NONE}, - {0x17, DISABLED, NONE} -#endif -#if 0 /* tyan guinness */ - /* mask, trigger, polarity, destination, delivery, vector */ - {0x00, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|ExtINT|0x0, ALL}, - {0x01, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x1, ALL}, - {0x02, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x0, ALL}, - {0x03, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x3, ALL}, - {0x04, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x4, ALL}, - {0x05, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x5, ALL}, - {0x06, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x6, ALL}, - {0x07, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x7, ALL}, - {0x08, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x8, ALL}, - {0x09, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0x9, ALL}, - {0x0a, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0xa, ALL}, - {0x0b, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0xb, ALL}, - {0x0c, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0xc, ALL}, - {0x0d, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0xd, ALL}, - {0x0e, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0xe, ALL}, - {0x0f, ENABLED|TRIGGER_EDGE|POLARITY_HIGH|LOGICAL_DEST|INT|0xf, ALL}, - {0x10, ENABLED|TRIGGER_LEVEL|POLARITY_LOW|LOGICAL_DEST|INT|0x10, ALL}, - {0x11, ENABLED|TRIGGER_LEVEL|POLARITY_LOW|LOGICAL_DEST|INT|0x11, ALL}, - {0x12, ENABLED|TRIGGER_LEVEL|POLARITY_LOW|LOGICAL_DEST|INT|0x12, ALL}, - {0x13, ENABLED|TRIGGER_LEVEL|POLARITY_LOW|LOGICAL_DEST|INT|0x13, ALL}, - {0x14, DISABLED, NONE}, - {0x14, DISABLED, NONE}, - {0x15, DISABLED, NONE}, - {0x16, DISABLED, NONE}, - {0x17, DISABLED, NONE}, -#endif -#if 1 /* mask, trigger, polarity, destination, delivery, vector */ {0x00, DISABLED, NONE}, {0x01, DISABLED, NONE}, @@ -105,7 +50,6 @@ struct ioapicreg ioapicregvalues[] = { {0x15, DISABLED, NONE}, {0x16, DISABLED, NONE}, {0x17, DISABLED, NONE}, -#endif }; void setup_ioapic(void) @@ -117,6 +61,13 @@ void setup_ioapic(void) struct ioapicreg *a = ioapicregvalues; l = (unsigned long *) nvram; +#if defined(i786) + /* For the pentium 4 and above apic deliver their interrupts + * on the front side bus, enable that. + */ + l[0] = 0x03; + l[4] = 1; +#endif /* i786 */ for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]); i++, a++) { l[0] = (a->reg * 2) + 0x10; diff --git a/src/config/Config b/src/config/Config new file mode 100644 index 0000000000..dac20707cc --- /dev/null +++ b/src/config/Config @@ -0,0 +1,47 @@ +## This is Architecture independant part of the makefile + +makedefine CC:=gcc +makedefine CPP:= gcc -x assembler-with-cpp -DASSEMBLY -E +makedefine LIBGCC_FILE_NAME := $(shell $(CC) -print-libgcc-file-name) +makedefine GCC_INC_DIR := $(shell $(CC) -print-search-dirs | sed -ne "s/install: \(.*\)/\1include/gp") + +makedefine CPPFLAGS := -I$(TOP)/src/include -I$(TOP)/src/arch/$(ARCH)/include -I$(GCC_INC_DIR) $(CPUFLAGS) +makedefine CFLAGS := $(CPU_OPT) $(CPPFLAGS) -Os -nostdinc -nostdlib -fno-builtin -Wall + +makerule ldscript.ld : ldoptions $(LDSUBSCRIPTS-1) ; echo "INCLUDE ldoptions" > $@ ; for file in $(LDSUBSCRIPTS-1) ; do echo "INCLUDE $$file" >> $@ ; done + +makerule cpuflags : Makefile.settings ; perl -e 'print "CPUFLAGS :=\n"; foreach $$var (split(" ", $$ENV{VARIABLES})) { if (exists($$ENV{$$var})) { print "CPUFLAGS += -D$$var" . (length($$ENV{$$var})?"=\x27$$ENV{$$var}\x27":"") ."\n"} else { print "CPUFLAGS += -U$$var\n"} }' > $@ + +makerule ldoptions : Makefile.settings ; perl -e 'foreach $$var (split(" ", $$ENV{VARIABLES})) { if ($$ENV{$$var} =~ m/^(0x[0-9a-fA-F]+|0[0-7]+|[0-9]+)$$/) { print "$$var = $$ENV{$$var};\n"; }}' > $@ + +makerule linuxbios.strip: linuxbios ; objcopy -O binary linuxbios linuxbios.strip + +makerule linuxbios.o : crt0.o linuxbios.a $(LIBGCC_FILE_NAME) ; $(CC) -nostdlib -r -o $@ crt0.o linuxbios.a $(LIBGCC_FILE_NAME) + + +makerule linuxbios: linuxbios.o ldscript.ld ; $(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld linuxbios.o +addaction linuxbios nm -n linuxbios > linuxbios.map + +makerule linuxbios.a : $(OBJECTS-1) ; rm -f linuxbios.a +addaction linuxbios.a ar cr linuxbios.a $(OBJECTS-1) + +makerule crt0.s: crt0.S ; $(CPP) $(CPPFLAGS) -I$(TOP)/src $< > crt0.s + +makerule crt0.o : crt0.s; $(CC) $(CPU_OPT) -c crt0.s + +makerule etags: $(SOURCES) ; etags $(SOURCES) +makerule tags: $(SOURCES) ; ctags $(SOURCES) +makerule documentation: $(SOURCES) ; doxygen LinuxBIOSDoc.config + +makerule clean : ; rm -f linuxbios.* *~ +addaction clean rm -f linuxbios +addaction clean rm -f ldoptions cpuflags ldscript.ld +addaction clean rm -f a.out *.s *.l *.o +addaction clean rm -f TAGS tags +addaction clean rm -f docipl + +# do standard config files that the user need not specify +# for now, this is just 'lib', but it may be more later. +dir /src/lib +dir /src/boot +dir /src/rom diff --git a/src/cpu/i386/entry16.inc b/src/cpu/i386/entry16.inc index d9906c3096..e7692a419d 100644 --- a/src/cpu/i386/entry16.inc +++ b/src/cpu/i386/entry16.inc @@ -36,6 +36,10 @@ EXT(_start): jmp _realstart * at 0x18; these are Linux-compatible. */ +#ifndef CACHE_RAM_BASE +#define CACHE_RAM_BASE 0 +#endif + /** GDT. we have modified this from the original freebios to make it * compatible with linux. This puts text at seg 0x10 and data at 0x18 */ @@ -46,16 +50,16 @@ EXT(gdtptr): .long gdt /* we know the offset */ gdt: .word 0x0000, 0x0000 /* dummy */ - .byte 0x0, 0x0, 0x0, 0x0 - - .word 0x0000, 0x0000 /* dummy */ - .byte 0x0, 0x0, 0x0, 0x0 + .byte 0x00, 0x00, 0x00, 0x00 + + .word 0xffff, (CACHE_RAM_BASE & 0xffff) /* flat offset data segment */ + .byte ((CACHE_RAM_BASE >> 16)& 0xff), 0x93, 0xcf, ((CACHE_RAM_BASE >> 24) & 0xff) .word 0xffff, 0x0000 /* flat code segment */ - .byte 0x0, 0x9b, 0xcf, 0x0 + .byte 0x00, 0x9b, 0xcf, 0x00 .word 0xffff, 0x0000 /* flat data segment */ - .byte 0x0, 0x93, 0xcf, 0x0 + .byte 0x00, 0x93, 0xcf, 0x00 _realstart: diff --git a/src/cpu/i786/Config b/src/cpu/i786/Config new file mode 100644 index 0000000000..59f9845cfb --- /dev/null +++ b/src/cpu/i786/Config @@ -0,0 +1 @@ +option i786 diff --git a/src/cpu/i786/cache_ram_fini.inc b/src/cpu/i786/cache_ram_fini.inc new file mode 100644 index 0000000000..27b6554d52 --- /dev/null +++ b/src/cpu/i786/cache_ram_fini.inc @@ -0,0 +1,39 @@ +#if defined(CACHE_RAM_BASE) && defined(CACHE_RAM_SIZE) + /* Note: We cannot be running from simulated ram in + * this code. If we are evil things will happen. + */ + + /* Disable the cache */ + movl %cr0, %eax + orl $0x40000000, %eax + movl %eax, %cr0 + + /* Flush everything that is left in the cache, + * We don't want random writes to memory to occur later on. + */ + invd + + /* Disable the cache ram mtrr */ + movl $0x204, %ecx + xorl %eax, %eax + xorl %edx, %edx + wrmsr + + movl $0x205, %ecx + xorl %eax, %eax + xorl %edx, %edx + wrmsr + + /* Reenable the cache now that the mtrr is cleared */ + movl %cr0, %eax + andl $0x9fffffff, %eax + movl %eax, %cr0 + + /* Reload the normal data segments */ + movw $0x18, %ax + movw %ax, %ds + movw %ax, %es + movw %ax, %ss + movw %ax, %fs + movw %ax, %gs +#endif diff --git a/src/cpu/i786/cache_ram_init.inc b/src/cpu/i786/cache_ram_init.inc new file mode 100644 index 0000000000..4fd8740eb5 --- /dev/null +++ b/src/cpu/i786/cache_ram_init.inc @@ -0,0 +1,42 @@ +#if defined(CACHE_RAM_BASE) && defined(CACHE_RAM_SIZE) + /* Disable the cache while we set up the cache ram MTRR */ + movl %cr0, %eax + orl $0x40000000, %eax + movl %eax, %cr0 + + /* Set up an mtrr in write-back mode over some arbitrary + * location. As long as we do not get a capacity miss, + * or a multiprocessor conflict miss this should allow us to + * function as if we have memory even when it hasn't been + * enabled yet. + */ + movl $0x204, %ecx /* mtrr[0] physical base register */ + xorl %edx, %edx + movl $(CACHE_RAM_BASE | 0x006), %eax + wrmsr + + movl $0x205, %ecx /* mtrr[0] physical mask register */ + movl $0x0000000f, %edx + movl $(~(CACHE_RAM_SIZE - 1) | 0x800), %eax + wrmsr + + /* Reenable the cache now that the mtrr is set up */ + movl %cr0, %eax + andl $0x9fffffff, %eax + movl %eax, %cr0 + + /* Force cache ram area into cache */ + movl $CACHE_RAM_BASE, %esi + movl $(CACHE_RAM_BASE + CACHE_RAM_SIZE), %edi +1: movl (%esi), %eax + addl $4, %esi + movl %eax, (%esi) + cmpl %esi, %edi + jnz 1b + + /* Load a different set of data segments */ + movw $0x08, %ax + movw %ax, %ds + movw %ax, %es + movw %ax, %ss +#endif \ No newline at end of file diff --git a/src/cpu/i786/cache_ram_start.inc b/src/cpu/i786/cache_ram_start.inc new file mode 100644 index 0000000000..605e609b6b --- /dev/null +++ b/src/cpu/i786/cache_ram_start.inc @@ -0,0 +1,25 @@ + /* copy data segment from FLASH ROM to CACHE */ + movl $(EXT(_ldata) - CACHE_RAM_BASE), %esi + movl $EXT(_data), %edi + movl $(EXT(_eldata) - CACHE_RAM_BASE), %ecx + subl %esi, %ecx + jz 1f /* should not happen */ + rep + movsb +1: + + /** clear bss */ + movl $EXT(_bss), %edi + movl $EXT(_ebss), %ecx + subl %edi, %ecx + jz 1f + xorl %eax, %eax + rep + stosb +1: + + /* set new stack */ + movl $(_stack + STACK_SIZE), %esp + + call cache_ram_start + diff --git a/src/cpu/i786/earlymtrr.inc b/src/cpu/i786/earlymtrr.inc new file mode 100644 index 0000000000..21553489a4 --- /dev/null +++ b/src/cpu/i786/earlymtrr.inc @@ -0,0 +1,108 @@ +#include + +/* The fixed and variable MTRRs are powered-up with random values, clear them to + * MTRR_TYPE_UNCACHABLE for safty reason + */ + +earlymtrr_start: + xorl %eax, %eax # clear %eax and %edx + xorl %edx, %edx # + movl $fixed_mtrr_msr, %esi + +clear_fixed_var_mtrr: + lodsl (%esi), %eax + testl %eax, %eax + jz clear_fixed_var_mtrr_out + + movl %eax, %ecx + xorl %eax, %eax + wrmsr + + jmp clear_fixed_var_mtrr +clear_fixed_var_mtrr_out: + +#ifdef MEMORY_HOLE +set_fixed_mtrr: + /* enable Write Back Cache for 0-640KB */ + movl $MTRRfix64K_00000_MSR, %ecx + rdmsr + movl $0x06060606, %edx + movl $0x06060606, %eax + wrmsr + + movl $MTRRfix16K_80000_MSR, %ecx + rdmsr + movl $0x06060606, %edx + movl $0x06060606, %eax + wrmsr +#endif /* MEMORY_HOLE */ + +set_var_mtrr: +#if 0 + /* enable caching for 0 - 128MB using variable mtrr */ + movl $0x200, %ecx + rdmsr + andl $0xfffffff0, %edx + orl $0x00000000, %edx + andl $0x00000f00, %eax + orl $0x00000006, %eax + wrmsr + + movl $0x201, %ecx + rdmsr + andl $0xfffffff0, %edx + orl $0x0000000f, %edx + andl $0x000007ff, %eax + orl $0xf0000800, %eax + wrmsr +#endif + +#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE) + /* enable write protect caching so we can do execute in place + * on the flash rom. + */ + movl $0x202, %ecx + xorl %edx, %edx + movl $(XIP_ROM_BASE | 0x005), %eax + wrmsr + + movl $0x203, %ecx + movl $0x0000000f, %edx + movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax + wrmsr +#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */ + +enable_mtrr: + /* Set the default memory type and enable fixed and variable MTRRs */ + movl $0x2ff, %ecx + xorl %edx, %edx +#ifdef MEMORY_HOLE + /* Enable Fixed and Variable MTRRs */ + movl $0x00000c00, %eax +#else + /* Enable Variable MTRRs */ + movl $0x00000800, %eax +#endif /* MEMORY_HOLE */ + wrmsr + + + /* enable cache */ + movl %cr0, %eax + andl $0x9fffffff,%eax + movl %eax, %cr0 + + jmp earlymtrr_end + +fixed_mtrr_msr: + .long 0x250, 0x258, 0x259 + .long 0x268, 0x269, 0x26A + .long 0x26B, 0x26C, 0x26D + .long 0x26E, 0x26F +var_mtrr_msr: + .long 0x200, 0x201, 0x202, 0x203 + .long 0x204, 0x205, 0x206, 0x207 + .long 0x208, 0x209, 0x20A, 0x20B + .long 0x20C, 0x20D, 0x20E, 0x20F + .long 0x000 /* NULL, end of table */ + +earlymtrr_end: diff --git a/src/cpu/p6/mtrr.c b/src/cpu/p6/mtrr.c index ae4db039a8..802ca5c27b 100644 --- a/src/cpu/p6/mtrr.c +++ b/src/cpu/p6/mtrr.c @@ -109,6 +109,7 @@ static unsigned char fixed_mtrr_values[][4] = { {ROM, ROM, ROM, ROM}, {ROM, ROM, ROM, ROM}, }; #else + static unsigned char fixed_mtrr_values[][4] = { /* MTRRfix64K_00000_MSR, defines memory range from 0KB to 512 KB, each byte cover 64KB area */ {RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM}, @@ -143,6 +144,7 @@ static unsigned char fixed_mtrr_values[][4] = { /* MTRRfix4K_F8000_MSR, defines memory range from F8000 to 100000, each byte cover 4KB area */ {ROM, ROM, ROM, ROM}, {ROM, ROM, ROM, ROM}, }; + #endif #undef FB diff --git a/src/include/logbuf_subr.h b/src/include/logbuf_subr.h new file mode 100644 index 0000000000..fcb4363ff4 --- /dev/null +++ b/src/include/logbuf_subr.h @@ -0,0 +1,4 @@ +#ifndef LOGBUF_SUBR_H +#define LOGBUF_SUBR_H + +#endif /* LOGBUF_SUBR_H */ diff --git a/src/include/pci_ids.h b/src/include/pci_ids.h index 03c61a3d06..b033869406 100644 --- a/src/include/pci_ids.h +++ b/src/include/pci_ids.h @@ -1205,6 +1205,15 @@ #define PCI_DEVICE_ID_INTEL_82801AB_5 0x2425 #define PCI_DEVICE_ID_INTEL_82801AB_6 0x2426 #define PCI_DEVICE_ID_INTEL_82801AB_8 0x2428 + +#define PCI_DEVICE_ID_INTEL_82801BA_1E0 0x244e +#define PCI_DEVICE_ID_INTEL_82801BA_1F0 0x2440 +#define PCI_DEVICE_ID_INTEL_82801BA_1F1 0x244b +#define PCI_DEVICE_ID_INTEL_82801BA_1F2 0x2442 +#define PCI_DEVICE_ID_INTEL_82801BA_1F3 0x2443 +#define PCI_DEVICE_ID_INTEL_82801BA_1F4 0x2444 +#define PCI_DEVICE_ID_INTEL_82801BA_1F5 0x2445 + #define PCI_DEVICE_ID_INTEL_82820FW_0 0x2440 #define PCI_DEVICE_ID_INTEL_82820FW_1 0x2442 #define PCI_DEVICE_ID_INTEL_82820FW_2 0x2443 diff --git a/src/include/subr.h b/src/include/subr.h index 97c868f81e..dc065db73b 100644 --- a/src/include/subr.h +++ b/src/include/subr.h @@ -5,6 +5,9 @@ void displayinit(void); void display(char msg[]); +void display_tx_byte(unsigned char byte); +void display_tx_break(void); + void error(char errmsg[]); void post_code(uint8_t value); diff --git a/src/include/video_subr.h b/src/include/video_subr.h new file mode 100644 index 0000000000..291a306a38 --- /dev/null +++ b/src/include/video_subr.h @@ -0,0 +1,7 @@ +#ifndef VIDEO_SUBR_H +#define VIDEO_SUBR_H + +void video_init(void); +void video_tx_byte(unsigned char byte); + +#endif /* VIDEO_SUBR_H */ diff --git a/src/lib/Config b/src/lib/Config index d53b1dc473..94e28f88b2 100644 --- a/src/lib/Config +++ b/src/lib/Config @@ -2,7 +2,9 @@ object linuxbiosmain.o object linuxpci.o object newpci.o object printk.o -object serial_subr.o +object serial_subr.o SERIAL_CONSOLE +object video_subr.o VIDEO_CONSOLE +object logbuf_subr.o LOGBUF_CONSOLE object subr.o object vsprintf.o object memset.o diff --git a/src/lib/logbuf_subr.c b/src/lib/logbuf_subr.c new file mode 100644 index 0000000000..92723c1461 --- /dev/null +++ b/src/lib/logbuf_subr.c @@ -0,0 +1,14 @@ +#include + +#define LOGBUF_SIZE = 1024; + +// KEEP THIS GLOBAL. +// I need the address so I can watch it with the ARIUM hardware. RGM. +char logbuf[LOGBUF_SIZE]; +int logbuf_offset = 0; + +void logbuf_tx_byte(unsigned char byte) +{ + logbuf[logbuf_offset] = byte; + logbuf_offset = (logbuf_offset +1) % LOGBUF_SIZE; +} diff --git a/src/lib/newpci.c b/src/lib/newpci.c index 5ad9862b10..a8131ffa79 100644 --- a/src/lib/newpci.c +++ b/src/lib/newpci.c @@ -750,9 +750,9 @@ void enable_resources(struct pci_bus *bus) u16 command; pci_read_config_word(curdev, PCI_COMMAND, &command); command |= curdev->command; - pci_write_config_word(curdev, PCI_COMMAND, command); - printk_debug("DEV Set command bus 0x%x devfn 0x%x to 0x%x\n", + printk_debug("DEV Set command bus 0x%02x devfn 0x%02x to 0x%02x\n", curdev->bus->number, curdev->devfn, command); + pci_write_config_word(curdev, PCI_COMMAND, command); } } diff --git a/src/lib/printk.c b/src/lib/printk.c index 906845cb42..5b36d941e3 100644 --- a/src/lib/printk.c +++ b/src/lib/printk.c @@ -12,12 +12,9 @@ static char rcsid[] = "$Id$"; //typedef void * va_list; #include +#include #include -// KEEP THIS GLOBAL. -// I need the address so I can watch it with the ARIUM hardware. RGM. -char log_buf[1024]; - /* printk's without a loglevel use this.. */ #define DEFAULT_MESSAGE_LOGLEVEL 4 /* BIOS_WARNING */ @@ -36,7 +33,7 @@ int minimum_console_loglevel = MINIMUM_CONSOLE_LOGLEVEL; int default_console_loglevel = DEFAULT_CONSOLE_LOGLEVEL; void display(char*); -extern int vsprintf(char *buf, const char *, va_list); +extern int vtxprintf(void (*)(unsigned char), const char *, va_list); spinlock_t console_lock = SPIN_LOCK_UNLOCKED; @@ -52,10 +49,10 @@ int do_printk(int msg_level, const char *fmt, ...) spin_lock(&console_lock); va_start(args, fmt); - i = vsprintf(log_buf, fmt, args); /* hopefully i < sizeof(log_buf)-4 */ + i = vtxprintf(display_tx_byte, fmt, args); va_end(args); - display(log_buf); + display_tx_break(); spin_unlock(&console_lock); diff --git a/src/lib/serial_subr.c b/src/lib/serial_subr.c index f417973695..4b5ffe6cc4 100644 --- a/src/lib/serial_subr.c +++ b/src/lib/serial_subr.c @@ -18,6 +18,14 @@ static char rcsid[] = "$Id$"; #define TTYS0_DIV (115200/TTYS0_BAUD) +/* Line Control Settings */ +#ifndef TTYS0_LCS +/* Set 8bit, 1 stop bit, no parity */ +#define TTYS0_LCS 0x3 +#endif + +#define UART_LCS TTYS0_LCS + /* Data */ #define UART_RBR 0x00 #define UART_TBR 0x00 @@ -36,10 +44,6 @@ static char rcsid[] = "$Id$"; #define UART_MSR 0x06 #define UART_SCR 0x07 -#ifndef TTYS0_BAUD -#define TTYS0_BAUD 115200 -#endif - static inline int uart_can_tx_byte(unsigned base_port) { return inb(base_port + UART_LSR) & 0x20; @@ -141,10 +145,10 @@ inline void uart_init(unsigned base_port, unsigned divisor) /* enable fifo's */ outb(0x01, base_port + UART_FCR); /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x83, base_port + UART_LCR); + outb(0x80 | UART_LCS, base_port + UART_LCR); outb(divisor & 0xFF, base_port + UART_DLL); outb((divisor >> 8) & 0xFF, base_port + UART_DLM); - outb(0x03, base_port + UART_LCR); + outb(UART_LCS, base_port + UART_LCR); } void ttys0_init(void) diff --git a/src/lib/subr.c b/src/lib/subr.c index 23bf10aa46..837d7f6aa0 100644 --- a/src/lib/subr.c +++ b/src/lib/subr.c @@ -18,63 +18,18 @@ static char rcsid[] = "$Id$"; #ifdef SERIAL_CONSOLE #include #endif +#ifdef VIDEO_CONSOLE +#include +#endif +#ifdef LOGBUF_CONSOLE +#include +#endif -#ifdef VIDEO_BIOS_WORKS - -# error the video display code has not been tested - -// kludgy but this is only used here ... -static char *vidmem; /* The video buffer, should be replaced by symbol in ldscript.ld */ -static int video_line, video_col; - -#define LINES 25 /* Number of lines and */ -#define COLS 80 /* columns on display */ -#define VIDBUFFER 0x20000; - -static void video_init(void) -{ - video_line = 0; - video_col = 0; - vidmem = (char *) VIDBUFFER; - memset(vidmem, 0, 64*1024); -} -static void video_scroll(void) -{ - int i; - - memcpy(vidmem, vidmem + COLS * 2, (LINES - 1) * COLS * 2); - for (i = (LINES - 1) * COLS * 2; i < LINES * COLS * 2; i += 2) - vidmem[i] = ' '; -} - -static void video_tx_byte(unsigned char byte) -{ - if (byte == '\n') { - video_line++; - } - else if (byte == '\r') { - video_col = 0; - } - else { - videmem[((video_col + (video_line *COLS)) * 2)] = byte; - videmem[((video_col + (video_line *COLS)) * 2) +1] = 0x07; - video_col++; - } - if (video_col >= COLS) { - video_line++; - video_col = 0; - } - if (video_line >= LINES) { - video_scroll(); - video_line--; - } -} -#endif /* VIDEO_BIOS_WORKS */ // initialize the display void displayinit(void) { -#ifdef VIDEO_BIOS_WORKS +#ifdef VIDEO_CONSOLE video_init(); #endif #ifdef SERIAL_CONSOLE @@ -82,9 +37,9 @@ void displayinit(void) #endif } -void display_tx_byte(unsigned char byte) +static void __display_tx_byte(unsigned char byte) { -#ifdef VIDEO_BIOS_WORKS +#ifdef VIDEO_CONSOLE video_tx_byte(byte); #endif #ifdef SERIAL_CONSOLE @@ -93,17 +48,29 @@ void display_tx_byte(unsigned char byte) #ifdef SROM_CONSOLE srom_tx_byte(byte); #endif +#ifdef LOGBUF_CONSOLE + logbuf_tx_byte(byte); +#endif +} + +void display_tx_break(void) +{ +} + +void display_tx_byte(unsigned char byte) +{ + if (byte == '\n') + __display_tx_byte('\r'); + __display_tx_byte(byte); } void display(char *string) { while(*string) { - if (*string == '\n') { - display_tx_byte('\r'); - } display_tx_byte(*string); string++; } + display_tx_break(); } void error(char errmsg[]) diff --git a/src/lib/video_subr.c b/src/lib/video_subr.c new file mode 100644 index 0000000000..bdb7557f64 --- /dev/null +++ b/src/lib/video_subr.c @@ -0,0 +1,49 @@ +#include +# error the video display code has not been tested + +// kludgy but this is only used here ... +static char *vidmem; /* The video buffer, should be replaced by symbol in ldscript.ld */ +static int video_line, video_col; + +#define LINES 25 /* Number of lines and */ +#define COLS 80 /* columns on display */ +#define VIDBUFFER 0x20000; + +void video_init(void) +{ + video_line = 0; + video_col = 0; + vidmem = (char *) VIDBUFFER; + memset(vidmem, 0, 64*1024); +} +static void video_scroll(void) +{ + int i; + + memcpy(vidmem, vidmem + COLS * 2, (LINES - 1) * COLS * 2); + for (i = (LINES - 1) * COLS * 2; i < LINES * COLS * 2; i += 2) + vidmem[i] = ' '; +} + +void video_tx_byte(unsigned char byte) +{ + if (byte == '\n') { + video_line++; + } + else if (byte == '\r') { + video_col = 0; + } + else { + videmem[((video_col + (video_line *COLS)) * 2)] = byte; + videmem[((video_col + (video_line *COLS)) * 2) +1] = 0x07; + video_col++; + } + if (video_col >= COLS) { + video_line++; + video_col = 0; + } + if (video_line >= LINES) { + video_scroll(); + video_line--; + } +} diff --git a/src/lib/vsprintf.c b/src/lib/vsprintf.c index 7dc669e449..370a120f3e 100644 --- a/src/lib/vsprintf.c +++ b/src/lib/vsprintf.c @@ -88,12 +88,13 @@ __res = ((unsigned long) n) % (unsigned) base; \ n = ((unsigned long) n) / (unsigned) base; \ __res; }) -static char * number(char * str, long num, int base, int size, int precision +static int number(void (*tx_byte)(unsigned char byte), long num, int base, int size, int precision ,int type) { char c,sign,tmp[66]; const char *digits="0123456789abcdefghijklmnopqrstuvwxyz"; int i; + int count = 0; if (type & LARGE) digits = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ"; @@ -132,38 +133,35 @@ static char * number(char * str, long num, int base, int size, int precision size -= precision; if (!(type&(ZEROPAD+LEFT))) while(size-->0) - *str++ = ' '; + tx_byte(' '), count++; if (sign) - *str++ = sign; + tx_byte(sign), count++; if (type & SPECIAL) { if (base==8) - *str++ = '0'; + tx_byte('0'), count++; else if (base==16) { - *str++ = '0'; - *str++ = digits[33]; + tx_byte('0'), count++; + tx_byte(digits[33]), count++; } } if (!(type & LEFT)) while (size-- > 0) - *str++ = c; + tx_byte(c), count++; while (i < precision--) - *str++ = '0'; + tx_byte('0'), count++; while (i-- > 0) - *str++ = tmp[i]; + tx_byte(tmp[i]), count++; while (size-- > 0) - *str++ = ' '; - return str; + tx_byte(' '), count++; + return count; } -/* Forward decl. needed for IP address printing stuff... */ -int sprintf(char * buf, const char *fmt, ...); -int vsprintf(char *buf, const char *fmt, va_list args) +int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args) { int len; unsigned long num; int i, base; - char * str; const char *s; int flags; /* flags to number() */ @@ -172,10 +170,12 @@ int vsprintf(char *buf, const char *fmt, va_list args) int precision; /* min. # of digits for integers; max number of chars for from string */ int qualifier; /* 'h', 'l', or 'L' for integer fields */ + + int count; - for (str=buf ; *fmt ; ++fmt) { + for (count=0; *fmt ; ++fmt) { if (*fmt != '%') { - *str++ = *fmt; + tx_byte(*fmt), count++; continue; } @@ -234,10 +234,10 @@ int vsprintf(char *buf, const char *fmt, va_list args) case 'c': if (!(flags & LEFT)) while (--field_width > 0) - *str++ = ' '; - *str++ = (unsigned char) va_arg(args, int); + tx_byte(' '), count++; + tx_byte((unsigned char) va_arg(args, int)), count++; while (--field_width > 0) - *str++ = ' '; + tx_byte(' '), count++; continue; case 's': @@ -249,11 +249,11 @@ int vsprintf(char *buf, const char *fmt, va_list args) if (!(flags & LEFT)) while (len < field_width--) - *str++ = ' '; + tx_byte(' '), count++; for (i = 0; i < len; ++i) - *str++ = *s++; + tx_byte(*s++), count++; while (len < field_width--) - *str++ = ' '; + tx_byte(' '), count++; continue; case 'p': @@ -261,7 +261,7 @@ int vsprintf(char *buf, const char *fmt, va_list args) field_width = 2*sizeof(void *); flags |= ZEROPAD; } - str = number(str, + count += number(tx_byte, (unsigned long) va_arg(args, void *), 16, field_width, precision, flags); continue; @@ -270,15 +270,15 @@ int vsprintf(char *buf, const char *fmt, va_list args) case 'n': if (qualifier == 'l') { long * ip = va_arg(args, long *); - *ip = (str - buf); + *ip = count; } else { int * ip = va_arg(args, int *); - *ip = (str - buf); + *ip = count; } continue; case '%': - *str++ = '%'; + tx_byte('%'), count++; continue; /* integer number formats - set up the flags and "break" */ @@ -299,9 +299,9 @@ int vsprintf(char *buf, const char *fmt, va_list args) break; default: - *str++ = '%'; + tx_byte('%'), count++; if (*fmt) - *str++ = *fmt; + tx_byte(*fmt), count++; else --fmt; continue; @@ -316,10 +316,27 @@ int vsprintf(char *buf, const char *fmt, va_list args) num = va_arg(args, int); else num = va_arg(args, unsigned int); - str = number(str, num, base, field_width, precision, flags); + count += number(tx_byte, num, base, field_width, precision, flags); } - *str = '\0'; - return str-buf; + return count; +} + +/* FIXME this global makes vsprintf non-reentrant + */ +static char *str_buf; +static void str_tx_byte(char byte) +{ + *str_buf = byte; + str_buf++; +} + +int vsprintf(char * buf, const char *fmt, va_list args) +{ + int i; + str_buf = buf; + i = vtxprintf(str_tx_byte, fmt, args); + str_buf = 0; + return i; } int sprintf(char * buf, const char *fmt, ...) diff --git a/src/mainboard/asus/cua/Config b/src/mainboard/asus/cua/Config index 945d76fd63..2dc8c43c73 100644 --- a/src/mainboard/asus/cua/Config +++ b/src/mainboard/asus/cua/Config @@ -5,6 +5,7 @@ ldscript cpu/i386/entry16.lds mainboardinit northbridge/acer/m1631/chipset_init.inc mainboardinit superio/acer/m1535/setup_serial.inc mainboardinit pc80/serial.inc + northbridge acer/m1631 southbridge acer/m1535 superio acer/m1535 diff --git a/src/mainboard/intel/l440gx/Config b/src/mainboard/intel/l440gx/Config index 2dc9718b3f..4c676d5c25 100644 --- a/src/mainboard/intel/l440gx/Config +++ b/src/mainboard/intel/l440gx/Config @@ -4,10 +4,12 @@ mainboardinit cpu/i386/entry16.inc ldscript cpu/i386/entry16.lds mainboardinit cpu/i386/reset16.inc ldscript cpu/i386/reset16.lds + mainboardinit northbridge/intel/440gx/reset_test.inc mainboardinit superio/NSC/pc87309/setup_serial.inc mainboardinit pc80/serial.inc + northbridge intel/440gx southbridge intel/piix4e mainboardinit cpu/p6/earlymtrr.inc diff --git a/src/mainboard/intel/l440gx/mainboard.c b/src/mainboard/intel/l440gx/mainboard.c index 16d9e888c5..b18902a115 100644 --- a/src/mainboard/intel/l440gx/mainboard.c +++ b/src/mainboard/intel/l440gx/mainboard.c @@ -28,20 +28,19 @@ void mainboard_fixup() u32 dword; for(i = 0; i < 8; i++) { pci_read_config_byte(host_bridge_pcidev, 0x60 +i, &byte); - printk_debug("DRB[i] = 0x%02x\n", byte); + printk_spew("DRB[i] = 0x%02x\n", byte); } pci_read_config_byte(host_bridge_pcidev, 0x57, &byte); - printk_debug("DRAMC = 0x%02x\n", byte); + printk_spew("DRAMC = 0x%02x\n", byte); pci_read_config_byte(host_bridge_pcidev, 0x74, &byte); - printk_debug("RPS = 0x%02x\n", byte); + printk_spew("RPS = 0x%02x\n", byte); pci_read_config_word(host_bridge_pcidev, 0x78, &word); - printk_debug("PGPOL = 0x%04x\n", word); + printk_spew("PGPOL = 0x%04x\n", word); pci_read_config_dword(host_bridge_pcidev, 0x50, &dword); - printk_debug("NBXCFG = 0x%04x\n", dword); + printk_spew("NBXCFG = 0x%04x\n", dword); } #endif -#if 1 printk_debug("Reset Control Register\n"); outb(((inb(0xcf9) & 0x04) | 0x02), 0xcf9); @@ -157,9 +156,8 @@ void mainboard_fixup() /* DEVRESJ */ pci_write_config_dword(pm_pcidev, 0x7c, 0); -#endif -#if 1 +#if 0 /* Verify that smi is disabled */ printk_debug("Testing SMI\r\n"); diff --git a/src/mainboard/pcchips/m754lmr/Config b/src/mainboard/pcchips/m754lmr/Config index 93568c057a..4b85935c2d 100644 --- a/src/mainboard/pcchips/m754lmr/Config +++ b/src/mainboard/pcchips/m754lmr/Config @@ -8,6 +8,7 @@ ldscript cpu/i386/entry16.lds mainboardinit superio/acer/m1535/setup_serial.inc mainboardinit pc80/serial.inc + northbridge acer/m1631 southbridge acer/m1535 superio acer/m1535 diff --git a/src/mainboard/supermicro/p4dc6/Config b/src/mainboard/supermicro/p4dc6/Config new file mode 100644 index 0000000000..209bec9173 --- /dev/null +++ b/src/mainboard/supermicro/p4dc6/Config @@ -0,0 +1,73 @@ +arch i386 +mainboardinit cpu/i386/entry16.inc +ldscript cpu/i386/entry16.lds +mainboardinit cpu/i386/reset16.inc +ldscript cpu/i386/reset16.lds + +#rambase 0x04000000 +biosbase 0xffff0000 +option XIP_ROM_BASE=0xffff0000 +option XIP_ROM_SIZE=0x10000 +option CACHE_RAM_BASE=0xfff70000 +option CACHE_RAM_SIZE=0x00010000 +option USE_CACHE_RAM=1 +nooption USE_DEFAULT_LAYOUT +#rambase 0xfff70000 +rambase 0x00000000 +option STACK_SIZE=0x2000 + + +#mainboardinit northbridge/amd/amd76x/reset_test.inc + +#mainboardinit southbridge/intel/82801/definitions.inc +#mainboardinit southbridge/intel/82801/disable_watchdog.inc +#mainboardinit southbridge/intel/82801/lpc_com1.inc +mainboardinit cpu/i786/earlymtrr.inc +mainboardinit superio/winbond/w83627hf/setup_serial.inc +mainboardinit pc80/serial.inc +#mainboardinit ram/ramtest.inc +#mainboardinit mainboard/supermicro/p4dc6/spin.inc +mainboardinit cpu/i786/cache_ram_init.inc +#mainboardinit mainboard/supermicro/p4dc6/cache_test.inc +mainboardinit cpu/i786/cache_ram_start.inc +mainboardinit cpu/i786/cache_ram_fini.inc + +northbridge intel/82860 +southbridge intel/82801 +southbridge intel/82806 + + +nsuperio winbond/w83627hf com1={1} com2={1} floppy=1 lpt=1 keyboard=1 + +option RAMTEST=1 +option NO_KEYBOARD +option ENABLE_FIXED_AND_VARIABLE_MTRRS +#option FINAL_MAINBOARD_FIXUP + +object cacheramtest.o +object mainboard.o +object mptable.o HAVE_MP_TABLE +object irq_tables.o HAVE_PIRQ_TABLE +#keyboard pc80 +dir ../../../pc80 + +# FIXME are the SMBUS DIMM locations documented anywhere? +option SMBUS_MEM_DEVICE_START=(0xa << 3) +option SMBUS_MEM_DEVICE_END=(SMBUS_MEM_DEVICE_START +3) +option SMBUS_MEM_DEVICE_INC=1 +option SIO_BASE=0x2e +#option SMP=1 +option IOAPIC=1 +option HAVE_MP_TABLE=1 +option HAVE_PIRQ_TABLE=1 +#option MAX_CPUS=2 +#option FINAL_MAINBOARD_FIXUP=1 +#option HAVE_HARD_RESET=1 +#option STACK_SIZE=0x10000 +#option XIP_ROM_SIZE=0x8000 +#option XIP_ROM_BASE=0xffff8000 +nooption MEMORY_HOLE + +cpu p5 +cpu p6 +cpu i786 diff --git a/src/mainboard/supermicro/p4dc6/cacheramtest.c b/src/mainboard/supermicro/p4dc6/cacheramtest.c new file mode 100644 index 0000000000..638fb65da0 --- /dev/null +++ b/src/mainboard/supermicro/p4dc6/cacheramtest.c @@ -0,0 +1,1154 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RAM(type, addr) (*((type *)((unsigned char*)((addr) - CACHE_RAM_BASE)))) + +#define SMBUS_BUS 0 +#define SMBUS_DEVFN ((0x1f << 3) + 3) + +#define LPC_BUS 0 +#define LPC_DEVFN ((0x1f << 3) + 0) + +#define ICH2HUB_BUS 0 +#define ICH2HUB_DEVFN ((0x1e << 3) + 0) + +#define I860MCH_BUS 0 +#define I860MCH_DEVFN ((0x00 << 3) + 0) + +#define I860HUBA_BUS 0 +#define I860HUBA_DEVFN ((0x01 << 3) + 0) + +#define I860HUBB_BUS 0 +#define I860HUBB_DEVFN ((0x02 << 3) + 0) + +#define SMBUS_MEM_DEVICE_0 (0xa << 3) + +static struct smbus_info{ + u32 base; +} smbus; + + +#define SMBHSTSTAT 0x0 +#define SMBHSTCTL 0x2 +#define SMBHSTCMD 0x3 +#define SMBXMITADD 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBBLKDAT 0x7 +#define SMBTRNSADD 0x9 +#define SMBSLVDATA 0xa +#define SMLINK_PIN_CTL 0xe +#define SMBUS_PIN_CTL 0xf + +void smbus_setup(void) +{ + u8 smbus_enable; + u16 smbus_func_enable; + + pcibios_write_config_dword(SMBUS_BUS, SMBUS_DEVFN, 0x20, 0x1000 | 1); + pcibios_write_config_byte(SMBUS_BUS, SMBUS_DEVFN, 0x40, 1); + pcibios_write_config_word(SMBUS_BUS, SMBUS_DEVFN, 0x4, 1); + + pcibios_read_config_dword(SMBUS_BUS, SMBUS_DEVFN, 0x20, &smbus.base); + pcibios_read_config_byte(SMBUS_BUS, SMBUS_DEVFN, 0x40, &smbus_enable); + pcibios_read_config_word(SMBUS_BUS, SMBUS_DEVFN, 0x4, &smbus_func_enable); + + printk_debug("smbus.base = %08x\n", smbus.base); + printk_debug("smbus.enable = %02x\n", smbus_enable); + printk_debug("smbus.func_enable = %04x\n", smbus_func_enable); + + smbus.base &= ~1; + printk_debug("\n"); + printk_debug("smbus.base = %08x\n", smbus.base); + printk_debug("smbus.enable = %02x\n", smbus_enable); + printk_debug("smbus.func_enable = %04x\n", smbus_func_enable); + + /* Disable interrupt generation */ + outb(0, smbus.base + SMBHSTCTL); +} + +static void smbus_wait_until_ready(void) +{ + while((inb(smbus.base + SMBHSTSTAT) & 1) == 1) { + /* nop */ + } +} +static void smbus_wait_until_done(void) +{ + unsigned char byte; + do { + byte = inb(smbus.base + SMBHSTSTAT); + } + while((byte &1) == 1); + while( (byte & ~(1|(1<<6))) == 0) { + byte = inb(smbus.base + SMBHSTSTAT); + } +} + + +#if 0 +static void smbus_print_error(unsigned char host_status_register) +{ + + printk_debug("smbus_error: 0x%02x\n", host_status_register); + if (host_status_register & (1 << 7)) { + printk_debug("Byte Done Status\n"); + } + if (host_status_register & (1 << 6)) { + printk_debug("In Use Status\n"); + } + if (host_status_register & (1 << 5)) { + printk_debug("SMBus Alert Status\n"); + } + if (host_status_register & (1 << 4)) { + printk_debug("Interrup/SMI# was Failed Bus Transaction\n"); + } + if (host_status_register & (1 << 3)) { + printk_debug("Bus Error\n"); + } + if (host_status_register & (1 << 2)) { + printk_debug("Device Error\n"); + } + if (host_status_register & (1 << 1)) { + printk_debug("Interrupt/SMI# was Successful Completion\n"); + } + if (host_status_register & (1 << 0)) { + printk_debug("Host Busy\n"); + } +} +#endif + +static int smbus_read_byte(unsigned device, unsigned address, unsigned char *result) +{ + unsigned char host_status_register; + unsigned char byte; + + smbus_wait_until_ready(); + + /* setup transaction */ + /* disable interrupts */ + outb(inb(smbus.base + SMBHSTCTL) & (~1), smbus.base + SMBHSTCTL); + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, smbus.base + SMBXMITADD); + /* set the command/address... */ + outb(address & 0xFF, smbus.base + SMBHSTCMD); + /* set up for a byte data read */ + outb((inb(smbus.base + SMBHSTCTL) & 0xE3) | (0x2 << 2), smbus.base + SMBHSTCTL); + + /* clear any lingering errors, so the transaction will run */ + outb(inb(smbus.base + SMBHSTSTAT), smbus.base + SMBHSTSTAT); + + /* clear the data byte...*/ + outb(0, smbus.base + SMBHSTDAT0); + + /* start the command */ + outb((inb(smbus.base + SMBHSTCTL) | 0x40), smbus.base + SMBHSTCTL); + + /* poll for transaction completion */ + smbus_wait_until_done(); + + host_status_register = inb(smbus.base + SMBHSTSTAT); +#if 1 + /* Ignore the In Use Status... */ + host_status_register &= ~(1 << 6); +#endif + + /* read results of transaction */ + byte = inb(smbus.base + SMBHSTDAT0); + +#if 0 + if (host_status_register != 0x02) { + smbus_print_error(host_status_register); + } +#endif + + *result = byte; + return host_status_register != 0x02; +} + +#define FLOPPY_DEVICE 0 +#define PARALLEL_DEVICE 1 +#define COM1_DEVICE 2 +#define COM2_DEVICE 3 +#define KBC_DEVICE 5 +#define CIR_DEVICE 6 +#define GAME_PORT_DEVICE 7 +#define GPIO_PORT2_DEVICE 8 +#define GPIO_PORT3_DEVICE 9 +#define ACPI_DEVICE 0xa +#define HW_MONITOR_DEVICE 0xb + +#define SIO_PORT 0x2e + +static void enter_pnp(void) +{ + outb(0x87, SIO_PORT); + outb(0x87, SIO_PORT); +} + +static void exit_pnp(void) +{ + outb(0xaa, SIO_PORT); +} + +static void write_config(unsigned char value, unsigned char reg) +{ + outb(reg, SIO_PORT); + outb(value, SIO_PORT +1); +} + +static unsigned char read_config(unsigned char reg) +{ + outb(reg, SIO_PORT); + return inb(SIO_PORT +1); +} +static void set_logical_device(int device) +{ + write_config(device, 0x07); +} + +static void set_enable(int enable) +{ + write_config(enable?0x1:0x0, 0x30); +#if 0 + if (enable) { + printk_debug("enabled superio device: %d\n", + read_config(0x07)); + } +#endif +} + +#if 0 +static void set_iobase0(unsigned iobase) +{ + write_config((iobase >> 8) & 0xff, 0x60); + write_config(iobase & 0xff, 0x61); +} + +static void set_iobase1(unsigned iobase) +{ + write_config((iobase >> 8) & 0xff, 0x62); + write_config(iobase & 0xff, 0x63); +} + +static void set_irq0(unsigned irq) +{ + write_config(irq, 0x70); +} + +static void set_irq1(unsigned irq) +{ + write_config(irq, 0x72); +} + +static void set_drq(unsigned drq) +{ + write_config(drq & 0xff, 0x74); +} +#endif + +static void select_rdram_i2c(void) +{ + unsigned char byte; + enter_pnp(); + byte = read_config(0x2b); + byte |= 0x30; + write_config(byte, 0x2b); + set_logical_device(GPIO_PORT2_DEVICE); + set_enable(1); + byte = read_config(0xf0); + byte &= ~(1 << 3); + write_config(byte, 0xf0); + exit_pnp(); +} + +#define I860_MCH_BUS 0 +#define I860_MCH_DEVFN 0 + +#define MCH_GAR0 0x40 +#define MCH_GAR1 0x41 +#define MCH_GAR2 0x42 +#define MCH_GAR3 0x43 +#define MCH_GAR4 0x44 +#define MCH_GAR5 0x45 +#define MCH_GAR6 0x46 +#define MCH_GAR7 0x47 +#define MCH_GAR8 0x48 +#define MCH_GAR9 0x49 +#define MCH_GAR10 0x4a +#define MCH_GAR11 0x4b +#define MCH_GAR12 0x4c +#define MCH_GAR13 0x4d +#define MCH_GAR14 0x4e +#define MCH_GAR15 0x4f +#define MCH_MCHCFG 0x50 +#define MCH_FDHC 0x58 +#define MCH_PAM0 0x59 +#define MCH_PAM1 0x5a +#define MCH_PAM2 0x5b +#define MCH_PAM3 0x5c +#define MCH_PAM4 0x5d +#define MCH_PAM5 0x5e +#define MCH_PAM6 0x5f +#define MCH_GBA0 0x60 +#define MCH_GBA1 0x62 +#define MCH_GBA2 0x64 +#define MCH_GBA3 0x66 +#define MCH_GBA4 0x68 +#define MCH_GBA5 0x6a +#define MCH_GBA6 0x6c +#define MCH_GBA7 0x6e +#define MCH_GBA8 0x70 +#define MCH_GBA9 0x72 +#define MCH_GBA10 0x74 +#define MCH_GBA11 0x76 +#define MCH_GBA12 0x78 +#define MCH_GBA13 0x7a +#define MCH_GBA14 0x7c +#define MCH_GBA15 0x7e +#define MCH_RDPS 0x88 +#define MCH_DRD 0x90 +#define MCH_RICM 0x94 +#define MCH_SMRAM 0x9d +#define MCH_ESMRAM 0x9e +#define MCH_RDT 0xbe +#define MCH_TOM 0xc4 +#define MCH_ERRSTS 0xc8 +#define MCH_ERRCMD 0xca +#define MCH_SMICMD 0xcc +#define MCH_SCICMD 0xce +#define MCH_DRAMRC 0xdc +#define MCH_DERRCTL 0xe2 +#define MCH_EAP 0xe4 + +#define RICM_BUSY (1 << 23) +#define RICM_DONE (1 << 27) + + +#define __S(NAME) NAME##_SHIFT +#define __B(NAME) NAME##_BITS +#define __BIT_MASK(SHIFT, BITS) ((1 << (BITS + SHIFT)) - (1 << (SHIFT))) +#define MASK(NAME) __BIT_MASK(__S(NAME), __B(NAME)) +#define NVAL(NAME, VAL) (MASK(NAME) & ((VAL) << __S(NAME))) +#define VAL(NAME, VALUE) ((MASK(NAME) & VALUE) >> __S(NAME)) + +#define RICM_CMD_SHIFT 0 +#define RICM_CMD_BITS 5 +#define RICM_ADDR_SHIFT 5 +#define RICM_ADDR_BITS 5 +#define RICM_REG_SHIFT 10 +#define RICM_REG_BITS 9 +#define RICM_BROADCAST_SHIFT 19 +#define RICM_BROADCAST_BITS 1 +#define RICM_CHANNEL_SHIFT 20 +#define RICM_CHANNEL_BITS 2 + +#define CMD_RDRAM_READ_REG 0 +#define CMD_RDRAM_WRITE_REG 1 +#define CMD_RDRAM_SET_RESET 2 +#define CMD_SET_FAST_CLK 4 +#define CMD_TEMP_CALIBRATE_ENABLE 5 +#define CMD_TEMP_CALIBRATE 6 +#define CMD_MRH_REDIRECT_NEXT_SIO 8 +#define CMD_MRH_STICK_SIO_RESET 9 +#define CMD_RDRAM_CLEAR_RESET 11 +#define CMD_RDRAM_CURRENT_CALIBRATION 16 +#define CMD_RDRAM_SIO_RESET 17 +#define CMD_RDRAM_POWERDOWN_EXIT 18 +#define CMD_RDRAM_POWERDOWN_ENTRY 19 +#define CMD_RDRAM_NAP_ENTRY 20 +#define CMD_RDRAM_NAP_EXIT 21 +#define CMD_RDRAM_REFRESH 22 +#define CMD_RDRAM_PRECHARGE 23 +#define CMD_MANUAL_CURRENT_CALIBRATION 24 +#define CMD_MCH_RAC_LOAD_RACA_CONFIG 25 +#define CMD_MCH_RAC_LOAD_RACB_CONFIG 26 +#define CMD_MCH_INITIALIZE_RAC 27 +#define CMD_MCH_RAC_CURRENT_CALIBRATION 28 +#define CMD_MCH_RAC_TEMP_CALIBRATE 29 +#define CMD_POWERUP_ALL_SEQUENCE 31 + +#define REG_INIT 0x21 +#define REG_TEST34 0x22 +#define REG_CNFGA 0x23 +#define REG_CNFGB 0x24 +#define REG_DEVID 0x40 +#define REG_REFB 0x41 +#define REG_REFR 0x42 +#define REG_CCA 0x43 +#define REG_CCB 0x44 +#define REG_NAPX 0x45 +#define REG_PDNXA 0x46 +#define REG_PDNX 0x47 +#define REG_TPARM 0x48 +#define REG_TFRM 0x49 +#define REG_TCDLY1 0x4a +#define REG_SKIP 0x4b +#define REG_TCYCLE 0x4c +#define REG_TEST77 0x4d +#define REG_TEST78 0x4e +#define REG_TEST79 0x4f + +#define BCAST 0xffff + +static void rdram_wait_until_ready(void) +{ + u32 ricm; + do { + pcibios_read_config_dword(I860_MCH_BUS, I860_MCH_DEVFN, MCH_RICM, &ricm); + } while(ricm & RICM_BUSY); +} + +struct rdram_reg_values { + u16 channel_a; + u16 channel_b; +}; + +static void __rdram_run_command(u8 channel, u16 sdevice_id, u16 reg, u16 command) +{ + u32 ricm; + int broadcast; + + broadcast = 0; + if (sdevice_id == BCAST) { + broadcast = 1; + sdevice_id = 0; + } + + /* Read the old register value and modify it */ + pcibios_read_config_dword(I860_MCH_BUS, I860_MCH_DEVFN, MCH_RICM, &ricm); + ricm &= ~(MASK(RICM_CHANNEL) | MASK(RICM_BROADCAST) | MASK(RICM_ADDR) | + MASK(RICM_REG) | MASK(RICM_CMD)); + ricm |= NVAL(RICM_CHANNEL, channel); + ricm |= NVAL(RICM_BROADCAST, broadcast); + ricm |= NVAL(RICM_ADDR, sdevice_id); + ricm |= NVAL(RICM_REG, reg); + ricm |= NVAL(RICM_CMD, command); + + /* Write the command */ + pcibios_write_config_dword(I860_MCH_BUS, I860_MCH_DEVFN, MCH_RICM, ricm); + + /* Start the command running */ + ricm |= RICM_BUSY; + pcibios_write_config_dword(I860_MCH_BUS, I860_MCH_DEVFN, MCH_RICM, ricm); + + /* Wait until the command completes */ + rdram_wait_until_ready(); + +} + +static void rdram_run_command(u8 channel, u16 sdevice_id, u16 command) +{ + /* Wait until the previous cmd completes */ + rdram_wait_until_ready(); + + /* Run the command */ + __rdram_run_command(channel, sdevice_id, 0, command); +} + +static void rdram_read_reg(u8 channel, u16 sdevice_id, u16 reg, struct rdram_reg_values *res) +{ + u32 drd; + + /* Wait until the previous cmd completes */ + rdram_wait_until_ready(); + + __rdram_run_command(channel, sdevice_id, reg, CMD_RDRAM_READ_REG); + + /* Read back the register value */ + pcibios_read_config_dword(I860_MCH_BUS, I860_MCH_DEVFN, MCH_DRD, &drd); + + res->channel_a = (drd >> 16) &0xffff; + res->channel_b = drd & 0xffff; + return; +} + + +static void rdram_write_reg(u8 channel, u16 sdevice_id, u16 reg, + u16 channel_a, u16 channel_b) +{ + u32 drd; + + /* Wait until the previous cmd completes */ + rdram_wait_until_ready(); + + + /* Write the data values */ + drd = (((u32)channel_a) << 16) | channel_b; + pcibios_write_config_dword(I860_MCH_BUS, I860_MCH_DEVFN, MCH_DRD, drd); + + __rdram_run_command(channel, sdevice_id, reg, CMD_RDRAM_WRITE_REG); + + /* Wait until the command completes */ + rdram_wait_until_ready(); + + return; +} + +u16 rdram_regs[] = { + REG_INIT, + REG_TEST34, + REG_CNFGA, + REG_CNFGB, + REG_DEVID, + REG_REFB, + REG_REFR, + REG_CCA, + REG_CCB, + REG_NAPX, + REG_PDNXA, + REG_PDNX, + REG_TPARM, + REG_TFRM, + REG_TCDLY1, + REG_SKIP, + REG_TCYCLE, + REG_TEST77, + REG_TEST78, + REG_TEST79, +}; +char *rdram_reg_names[] = { + "INIT", + "TEST34", + "CNFGA", + "CNFGB", + "DEVID", + "REFB", + "REFR", + "CCA", + "CCB", + "NAPX", + "PDNXA", + "PDNX", + "TPARM", + "TFRM", + "TCDLY1", + "SKIP", + "TCYCLE", + "TEST77", + "TEST78", + "TEST79", +}; + +static void set_sdevid(int rdram_devices) +{ + int i; + /* First disable the repeater and set every RDRAM to the + * maximum address I can address + */ + rdram_write_reg(0, BCAST, REG_INIT, 0x1f, 0x1f); + for(i = 0; i < rdram_devices; i++) { + /* Set SDEVID and reenable the repeater */ + rdram_write_reg(0, 0x1f, REG_INIT, + (1 << 7) | (i & 0x1f), (1 << 7) | (i & 0x1f)); + + } +} + +static void set_devid(int rdram_devices) +{ + int i; + for(i = 0; i < rdram_devices; i++) { + /* FIXME make this smarter */ + /* Initially set DEVID == SDEVID */ + if ((i % 4) != 5) { + rdram_write_reg(0, i, REG_DEVID, i, i ); + } else { + rdram_write_reg(0, i, REG_DEVID, 0x1f, i); + } + } +} + +static void set_init_bits(int rdram_devices) +{ + int i; + for(i = 0; i < rdram_devices; i++) { + /* Now that the chip is up and running setup the + * power management modes. + */ + rdram_write_reg(0, i, REG_INIT, + (1 << 9) | (1 << 7) | (1 << 6) | (i & 0x1f), + (1 << 9) | (1 << 7) | (1 << 6) | (i & 0x1f) + ); + } +} + +static void rdram_read_domain_initialization(int rdram_devices) +{ + /* FIXME Figure the rest of this out... */ + int i; + for(i = 0; i < rdram_devices; i++) { + struct rdram_reg_values values; + u16 tcdly1_a, tcdly1_b; + unsigned long addr, value; + addr = i*32*1024*1024; +#if 0 + RAM(unsigned long, addr) = addr; + value = RAM(unsigned long, addr); +#endif + /* Decrement TCDLY1 for every chip that doesn't have auto-skip=1 */ + rdram_read_reg(0, i, REG_SKIP, &values); + tcdly1_a = 2; + tcdly1_b = 2; + if (i >= 7) { + tcdly1_b = 1; + } + if (i >= 10) { + tcdly1_a = 1; + } + if (!(values.channel_a & (1 << 12))) { + tcdly1_a--; + } + if (!(values.channel_b & (1 << 12))) { + tcdly1_b--; + } + rdram_write_reg(0, i, REG_TCDLY1, tcdly1_a, tcdly1_b); +#if 0 + value = RAM(unsigned long, addr); +#endif + } +#if 1 + /* RDRAM Device Timing */ + pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_RDT, 0x8a); +#endif + +#if 0 + rdram_run_command(0, 0, CMD_MCH_RAC_LOAD_RACA_CONFIG); + rdram_run_command(0, 0, CMD_MCH_RAC_LOAD_RACB_CONFIG); +#endif + +} + +static void ndelay(unsigned long ns) +{ + unsigned long long count; + unsigned long long stop; + unsigned long long ticks; + + /* FIXME calibrate this... don't just estimage 2Ghz */ + ticks = ns << 1; + rdtscll(count); + stop = ticks + count; + while(stop > count) { + rdtscll(count); + } +} + +static void rdram_set_clear_reset(void) +{ + rdram_write_reg(0, BCAST, REG_TEST78, 0x04, 0x04); + rdram_write_reg(0, BCAST, REG_TEST34, 0x40, 0x40); + rdram_run_command(0, BCAST, CMD_RDRAM_SET_RESET); + /* FIXME Compute max of 16 * Tscycle or 2816 * Tcycle */ + ndelay(7040); + rdram_run_command(0, BCAST, CMD_RDRAM_CLEAR_RESET); + rdram_write_reg(0, BCAST, REG_TEST34, 0, 0); + rdram_write_reg(0, BCAST, REG_TEST78, 0, 0); +} + +/* + - ro CNFGA, CNFGB, + - ok REFB, REFR + - SKIP, TEST79 + TEST34, TEST78, + TEST77, + TCYCLE, + INIT, + DEVID, + PDNXA, PDNX, NAPX, TPARM, TCDLY1, TFRM, REG_CCA, REG, CCB +*/ +static void rdram_init(int rdram_devices) +{ + /* 3.1/3.2 RDRAM SIO reset */ + rdram_run_command(0, 0, CMD_RDRAM_SIO_RESET); + + /* 3.3 Clear TEST77 */ + rdram_write_reg(0, BCAST, REG_TEST77, 0, 0); + + /* 3.4 Write Tcycle */ + /* FIXME Hard coded as 400Mhz for now */ + rdram_write_reg(0, BCAST, REG_TCYCLE, 0x27, 0x27); + + /* 3.5 Set SDEVID */ + set_sdevid(rdram_devices); + + /* 3.6 Set DEVID */ + set_devid(rdram_devices); + + /* 3.7 Write PDNX, PDNXA Registers */ + /* FIXME don't hard code these timings... */ + rdram_write_reg(0, BCAST, REG_PDNXA, 0x7, 0x7); + rdram_write_reg(0, BCAST, REG_PDNX, 0x5, 0x5); + + /* 3.8 Write NAPX */ + /* FIXME don't hard code this timing */ + rdram_write_reg(0, BCAST, REG_NAPX, 0x525, 0x525); + + /* 3.9 Write TPARM */ + /* FIXME figure how to compute this initial timing. */ + rdram_write_reg(0, BCAST, REG_TPARM, 0x3a, 0x3a); + + /* 3.10 Write TCDLY1 Register */ + /* FIXME figure how to compute this initial timing. */ + rdram_write_reg(0, BCAST, REG_TCDLY1, 2, 2); + + /* 3.11 Write TFRM Register */ + /* FIXME refine the computation on this register. */ +#if 0 + rdram_write_reg(0, BCAST, REG_TFRM, 10, 10); +#else + rdram_write_reg(0, BCAST, REG_TFRM, 9, 9); +#endif + + /* 3.12 SETR/CLRR */ + rdram_set_clear_reset(); + + /* 3.13 Write CCA and CCB Registers */ + /* Program all Current controll registers with + * an initial approximation. 1/2 their maximum is recommended. + */ + /* FIXME figure out voltage assymetry */ + rdram_write_reg(0, BCAST, REG_CCA, 0x40, 0x40); + rdram_write_reg(0, BCAST, REG_CCB, 0x40, 0x40); + + /* 3.14 Powerdown Exit */ + /* FIXME not all RDRAMS models need this */ + rdram_run_command(0, BCAST, CMD_RDRAM_POWERDOWN_EXIT); + + /* 3.15 SETF */ + rdram_run_command(0, BCAST, CMD_SET_FAST_CLK); +} + +void mch_init(void) +{ + u8 byte; + u16 word; + u32 dword; + /* FIXME unhard code these values */ + /* Program Group Attribute Registers */ + /* 1KB pages, 2x16 banks, 128/144Mbit */ + pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR0, 0x92); + pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR1, 0x92); + pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR2, 0x92); + pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR3, 0x92); + /* Nothing.. */ + pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR4, 0x80); + pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR5, 0x80); + pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR6, 0x80); + pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR7, 0x80); + pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR8, 0x80); + pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR9, 0x80); + pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR10, 0x80); + pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR11, 0x80); + pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR12, 0x80); + pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR13, 0x80); + pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR14, 0x80); + pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GAR15, 0x80); + + /* Memory Controller Hub Configuration */ + /* 2 System Bus Stop Grant, 400Mhz, Non-ECC, MDA Not Present, Apic Enabled */ + pcibios_read_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_MCHCFG, &word); + word &= ~((7 << 13) | (1 << 9) | (3 << 7) | (1 << 5) | (1 << 0)); + word |= (1 << 13) | (1 << 11); + pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_MCHCFG, word); + + /* Fixed DRAM Hole Control */ + /* Disabled */ + pcibios_read_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_FDHC, &byte); + byte &= ~(1 << 7); + pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_FDHC, byte); + + /* Programmable Attribute Map */ + /* All Ram, Except the mandatory VGA hole */ + pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_PAM0, 0x30); + pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_PAM1, 0x33); + pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_PAM2, 0x33); + pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_PAM3, 0x33); + pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_PAM4, 0x33); + pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_PAM5, 0x33); + pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_PAM6, 0x33); + + /* RDRAM Device Group Boundary Addresses */ + /* 4 groups of 8*16 MB each */ + pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA0, (0<<11)|(8<<0)); + pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA1, (1<<11)|(16<<0)); + pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA2, (2<<11)|(24<<0)); + pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA3, (3<<11)|(32<<0)); + /* The rest of the groups are empty */ + pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA4, (4<<11)|(32<<0)); + pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA5, (5<<11)|(32<<0)); + pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA6, (6<<11)|(32<<0)); + pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA7, (7<<11)|(32<<0)); + pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA8, (8<<11)|(32<<0)); + pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA9, (9<<11)|(32<<0)); + pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA10, (10<<11)|(32<<0)); + pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA11, (11<<11)|(32<<0)); + pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA12, (12<<11)|(32<<0)); + pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA13, (13<<11)|(32<<0)); + pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA14, (14<<11)|(32<<0)); + pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_GBA15, (15<<11)|(32<<0)); + + /* RDRAM Deice Pool Sizeing Register */ + pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_RDPS, 0x0f); + + /* RDRAM Device Timing */ + pcibios_write_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, MCH_RDT, 0x8e); + + /* Top of Memory */ + pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_TOM, 0x2000); + + /* Error Command Register */ + /* Disable reporting errors for now */ + pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_ERRCMD, 0); + + /* SMI Command Register */ + /* Disable reporting errors for now */ + pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_SMICMD, 0); + + /* SCI Command Register */ + /* Disable reporting errors for now */ + pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_SCICMD, 0); + + /* RDRAM Device Refresh Control */ + pcibios_write_config_word(I860_MCH_BUS, I860_MCH_DEVFN, MCH_DRAMRC, 1); +}; + + +static void init_memory(void) +{ + int i; + int rdram_devices = 16; + u32 ricm; + /* 1. Start the clocks */ + rdram_run_command(0, 0, CMD_POWERUP_ALL_SEQUENCE); + + /* 2. RAC initialization */ + rdram_run_command(0, 0, CMD_MCH_INITIALIZE_RAC); + + /* 3. Rdram initialize */ + rdram_init(rdram_devices); + + /* 4. Initialize Memory Controller */ + mch_init(); + + /* 6.1 RDRAM Core Initialization */ + for(i = 0; i < 192; i++) { + rdram_run_command(0, BCAST, CMD_RDRAM_REFRESH); + } + + /* 5. Rdram Current Control */ + /* You can disable the final memory initialized bit + * to see if this is working and it isn't! + * It is close though. + */ +#if 1 + rdram_run_command(0, 0, CMD_MCH_RAC_CURRENT_CALIBRATION); +#endif +#if 0 + rdram_run_command(0, 0, CMD_MANUAL_CURRENT_CALIBRATION); +#endif + for(i = 0; i < 128; i++) { + rdram_run_command(0, BCAST, CMD_RDRAM_CURRENT_CALIBRATION); + } +#if 0 +#endif + rdram_run_command(0, BCAST, CMD_TEMP_CALIBRATE_ENABLE); + rdram_run_command(0, BCAST, CMD_TEMP_CALIBRATE); + + /* 6.2 RDRAM Read Domain Initialization */ +#if 1 + rdram_read_domain_initialization(rdram_devices); +#endif + + /* 7.0 Remaining init bits (LSR, NSR, PSR) */ + set_init_bits(rdram_devices); + + /* Final Set the memory initialized bit */ +#if 1 + pcibios_read_config_dword(I860_MCH_BUS, I860_MCH_DEVFN, MCH_RICM, &ricm); + ricm |= RICM_DONE; + pcibios_write_config_dword(I860_MCH_BUS, I860_MCH_DEVFN, + MCH_RICM, ricm); +#endif + +} + +static void ram_fill(unsigned long start, unsigned long stop) +{ + unsigned long addr; + /* + * Fill. + */ + printk_debug("DRAM fill: %08lx-%08lx\n", start, stop); + for(addr = start; addr < stop ; addr += 4) { + /* Display address being filled */ + if ((addr & 0xffff) == 0) + printk_debug("%08lx\r", addr); + RAM(unsigned long, addr) = addr; + }; + /* Display final address */ + printk_debug("%08lx\nDRAM filled\n", addr); + + +} + +static int ram_verify(unsigned long start, unsigned long stop, int max_errors) +{ + unsigned long addr; + int errors = 0; + /* + * Verify. + */ + printk_debug("DRAM verify: %08lx-%08lx\n", start, stop); + for(addr = start; addr < stop ; addr += 4) { + unsigned long value; + /* Display address being tested */ + if ((addr & 0xffff) == 0) + printk_debug("%08lx\r", addr); + value = RAM(unsigned long, addr); + if (value != addr) { + if (++errors <= max_errors) { + /* Display address with error */ + printk_debug("%08lx:%08lx\n", addr, value); + } + } + } + /* Display final address */ + printk_debug("%08lx\nDRAM verified %d/%d errors\n", + addr, errors, (stop - start)/4); + return errors; +} + + +static int ram_odd_verify(unsigned long start, unsigned long stop, int max_errors) +{ + unsigned long addr; + int errors = 0; + /* + * Verify. + */ + printk_debug("DRAM odd verify: %08lx-%08lx\n", start, stop); + for(addr = start; addr < stop ; addr += 4) { + unsigned long value; + /* Display address being tested */ + if ((addr & 0xffff) == 0) + printk_debug("%08lx\r", addr); + value = RAM(unsigned long, addr); + if (value != (addr ^ 0x20)) { + if (++errors < max_errors) { + /* Display address with error */ + printk_debug("%08lx:%08lx\n", addr, value); + } + } + } + /* Display final address */ + printk_debug("%08lx\nDRAM odd verified %d/%d errors\n", + addr, errors, (stop - start)/4); + return 0; +} + + +static int ramcheck(unsigned long start, unsigned long stop, int max_errors) +{ + int result; + /* + * This is much more of a "Is my DRAM properly configured?" + * test than a "Is my DRAM faulty?" test. Not all bits + * are tested. -Tyson + */ + printk_debug("Testing DRAM : %08lx-%08lx\n", + start, stop); + + ram_fill(start, stop); + result = ram_verify(start, stop, max_errors); + printk_debug("Done.\n"); + return result; +} + + +static int ramcheck2(unsigned long start, unsigned long stop, int max_errors) +{ + int result; + /* + * This is much more of a "Is my DRAM properly configured?" + * test than a "Is my DRAM faulty?" test. Not all bits + * are tested. -Tyson + */ + printk_debug("Testing DRAM : %08lx-%08lx\n", + start, stop); + + ram_fill(start, stop); + result = ram_odd_verify(start, stop, max_errors); + + printk_debug("Done.\n"); + return result; +} + +/* setting variable mtrr, comes from linux kernel source */ +static void set_var_mtrr(unsigned int reg, unsigned long base, unsigned long size, unsigned char type) +{ + unsigned int tmp; + + if (reg >= 8) + return; + + // it is recommended that we disable and enable cache when we + // do this. + /* Disable cache */ + /* Write back the cache and flush TLB */ + asm volatile ( + "movl %%cr0, %0\n\t" + "orl $0x40000000, %0\n\t" + "movl %0, %%cr0\n\t" + :"=r" (tmp) + ::"memory"); + + if (size == 0) { + /* The invalid bit is kept in the mask, so we simply clear the + relevant mask register to disable a range. */ + wrmsr (MTRRphysMask_MSR (reg), 0, 0); + } else { + /* Bit 32-35 of MTRRphysMask should be set to 1 */ + wrmsr (MTRRphysBase_MSR (reg), base | type, 0); + wrmsr (MTRRphysMask_MSR (reg), ~(size - 1) | 0x800, 0x0F); + } + + // turn cache back on. + asm volatile ("movl %%cr0, %0\n\t" + "andl $0x9fffffff, %0\n\t" + "movl %0, %%cr0\n\t":"=r" (tmp)::"memory"); + +} + +void cache_ram_start(void) +{ + int i,j; + int error; + error = 0; + /* displayinit MUST PRECEDE ALL PRINTK! */ + displayinit(); + printk_info("printk: Testing %d %s\n", 123, "testing!!!"); + printk_info("Finding PCI configuration type.\n"); + pci_set_method(); + printk_info("Setting up smbus controller\n"); + smbus_setup(); + printk_info("Selecting rdram i2c bus\n"); + select_rdram_i2c(); + +#if 0 + for(j = SMBUS_MEM_DEVICE_0; j < SMBUS_MEM_DEVICE_0 + 8; j++) { + int status = 0; + if ((j == 0x1b) || 0) { + printk_debug("skipping device: %02x\n", j); + continue; + } + printk_debug("smbus_device: %02x\n", j); + for(i = 0; (i < 256) && (status == 0); i++) { + unsigned char byte; + status = smbus_read_byte(j, i, &byte); + if (status != 0) { + printk_debug("bad device\n"); + continue; + } + printk_debug("0x%02x ", byte); + if ((i &0x0f) == 0x0f) { + printk_debug("\n"); + } + } + } + printk_debug("\n"); +#endif + init_memory(); + printk_debug("set_var_mtrr\n"); +#if 0 + set_var_mtrr(0, 0, 512*1024*1024, MTRR_TYPE_WRBACK); +#else + set_var_mtrr(0, 0, 512*1024*1024, MTRR_TYPE_WRCOMB); +#endif + printk_debug("set_var_mtrr done\n"); +#if 0 + error |= ramcheck(0x000f0000, 0x000f1000, 20); +#endif +#if 1 + error |= ramcheck( 0x00000000, 0x00000400, 20); + error |= ramcheck( 0x00000400, 0x00000800, 20); + error |= ram_verify( 0x00000000, 0x00000400, 20); + error |= ram_verify( 0x00000400, 0x00000800, 20); +#endif +#if 1 + { + unsigned long addr; + for(addr = 0; addr < 0x20000000; addr += 0x02000000) { + ram_fill(addr, addr + 0x400); + } + /* Do some dummy writes to flush a write cache, in the + * processor. + */ + ram_fill(0xc0000000, 0xc0000400); + for(addr = 0; addr < 0x20000000; addr += 0x02000000) { + ram_verify(addr, addr + 0x400, 1); + } + } +#endif +#if 0 + error |= ramcheck( 0x00000000, 0x00000400, 128); + error |= ramcheck2(0x00000000, 0x00000400, 128); + error |= ramcheck( 0x14000000, 0x14000400, 128); + error |= ramcheck2(0x14000000, 0x14000400, 128); +#endif +#if 0 + error |= ramcheck2(0x00100000, 0x00180000, 128); +#endif + error |= ramcheck(0x00000000, 0x00080000, 20); + error |= ramcheck(0x02000000, 0x02080000, 20); + error |= ramcheck(0x04000000, 0x04080000, 20); + error |= ramcheck(0x06000000, 0x06080000, 20); + error |= ramcheck(0x08000000, 0x08080000, 20); + error |= ramcheck(0x0a000000, 0x0a080000, 20); + error |= ramcheck(0x0c000000, 0x0c080000, 20); + + error |= ramcheck(0x0e000000, 0x0e080000, 20); + error |= ramcheck(0x10000000, 0x10080000, 20); + error |= ramcheck(0x12000000, 0x12080000, 20); + error |= ramcheck(0x14000000, 0x14080000, 20); + error |= ramcheck(0x16000000, 0x16080000, 20); + error |= ramcheck(0x18000000, 0x18080000, 20); + error |= ramcheck(0x1a000000, 0x1a080000, 20); + error |= ramcheck(0x1c000000, 0x1c080000, 20); + error |= ramcheck(0x1e000000, 0x1e080000, 20); +#if 0 + error |= ramcheck(0x00000000, 0x00080000, 20); +#endif +#if 1 + for(i = 0; i < 16; i++) { + for(j = 0; j < sizeof(rdram_regs)/sizeof(rdram_regs[0]); j++) { + struct rdram_reg_values values; + u16 reg = rdram_regs[j]; + rdram_read_reg(0, i, reg, &values); + printk_debug("rdram: %2d reg: %02x %10s a: 0x%04x b: 0x%04x\n", + i, reg, rdram_reg_names[j], values.channel_a, values.channel_b); + } + } +#endif +#if 1 + for(i = 0; i < 16; i++) { + printk_debug("%02x: ", i << 4); + for(j = 0; j < 16; j++) { + u8 byte; + u8 addr = (i << 4) | j; + pcibios_read_config_byte(I860_MCH_BUS, I860_MCH_DEVFN, addr, &byte); + printk_debug("%02x ", byte); + } + printk_debug("\n"); + } +#endif + if (error) while(1); +} diff --git a/src/mainboard/supermicro/p4dc6/irq_tables.c b/src/mainboard/supermicro/p4dc6/irq_tables.c new file mode 100644 index 0000000000..1370cf7f76 --- /dev/null +++ b/src/mainboard/supermicro/p4dc6/irq_tables.c @@ -0,0 +1,28 @@ +/* PCI: Interrupt Routing Table found at 0x4011ced0 size = 176 */ + +#include + +const struct irq_routing_table intel_irq_routing_table = { + 0x52495024, /* u32 signature */ + 0x0100, /* u16 version */ + 176, /* u16 Table size 32+(16*devices) up to 9 devices */ + 0x00, /* u8 Bus 0 */ + 0xf8, /* u8 Device 1, Function 0 */ + 0x1c00, /* u16 reserve IRQ for PCI */ + 0x8086, /* u16 Vendor */ + 0x7000, /* Device ID */ + 0x00000000, /* u32 miniport_data */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xb1, /* u8 checksum - mod 256 checksum must give zero */ + { /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, 0x10, {{0x62, 0xdeb8}, {0x62, 0xdeb8}, {0x62, 0xdeb8}, {0x62, 0xdeb8}}, 0x01, 0x00}, + {0x04, 0x40, {{0x68, 0xdeb8}, {0x69, 0xdeb8}, {0x6a, 0xdeb8}, {0x6b, 0xdeb8}}, 0x02, 0x00}, + {0x04, 0x38, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x03, 0x00}, + {0x04, 0x08, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}}, 0x04, 0x00}, + {0x04, 0x10, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}}, 0x05, 0x00}, + {0x04, 0x18, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}}, 0x06, 0x00}, + {0x04, 0x20, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x07, 0x00}, + {0x00, 0xf8, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x6b, 0xdeb8}, {0x63, 0xdeb8}}, 0x00, 0x00}, + {0x00, 0x08, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x00, 0x00} + } +}; diff --git a/src/mainboard/supermicro/p4dc6/mainboard.c b/src/mainboard/supermicro/p4dc6/mainboard.c new file mode 100644 index 0000000000..90663623b8 --- /dev/null +++ b/src/mainboard/supermicro/p4dc6/mainboard.c @@ -0,0 +1,10 @@ +#include +#include + +void mainboard_fixup(void) +{ + ich2_enable_ioapic(); + ich2_enable_serial_irqs(); + printk_notice("Please add a mainboard_fixup!\n"); + return; +} diff --git a/src/mainboard/supermicro/p4dc6/mptable.c b/src/mainboard/supermicro/p4dc6/mptable.c new file mode 100644 index 0000000000..732dda5f8d --- /dev/null +++ b/src/mainboard/supermicro/p4dc6/mptable.c @@ -0,0 +1,106 @@ +#include +#include +#include + +void smp_write_config_table(void *v, unsigned long * processor_map) +{ + int ioapicid = 0; + static const char sig[4] = "PCMP"; + static const char oem[8] = "LNXI "; + static const char productid[12] = "P4DC6 "; + struct mp_config_table *mc; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + + + smp_write_processors(mc, processor_map); + ioapicid = 2; + + smp_write_bus(mc, 0, "PCI "); + smp_write_bus(mc, 1, "PCI "); + smp_write_bus(mc, 2, "PCI "); + smp_write_bus(mc, 3, "PCI "); + smp_write_bus(mc, 4, "PCI "); + smp_write_bus(mc, 5, "ISA "); + + smp_write_ioapic(mc, 2, 0x11, 0xfec00000); + + + /* Onboard ich2 soutbhridge */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, (0x1f << 2)|3, 0x02, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, (0x1f << 2)|2, 0x02, 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, (0x1f << 2)|1, 0x02, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x00, (0x1f << 2)|0, 0x02, 0x10); + + /* Onboard PCI NIC */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + 0x04, (4 <<2)|0, 0x02, 0x10); + + /* ISA backward compatibility interrupts */ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + 0x05, 0x00, 0x02, 0x00); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + 0x05, 0x01, 0x02, 0x01); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + 0x05, 0x00, 0x02, 0x02); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + 0x05, 0x03, 0x02, 0x03); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + 0x05, 0x04, 0x02, 0x04); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + 0x05, 0x06, 0x02, 0x06); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + 0x05, 0x07, 0x02, 0x07); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, + 0x05, 0x08, 0x02, 0x08); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + 0x05, 0x09, 0x02, 0x09); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + 0x05, 0x0d, 0x02, 0x0d); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + 0x05, 0x0e, 0x02, 0x0e); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + 0x05, 0x0f, 0x02, 0x0f); + + /* Standard local interrupt assignments */ + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + 0x00, 0x00, MP_APIC_ALL, 0x00); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, + 0x00, 0x00, MP_APIC_ALL, 0x01); + + + /* There is no extension information... */ + + /* Compute the checksums */ + mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + printk_debug("Wrote the mp table end at: %p - %p\n", + mc, smp_next_mpe_entry(mc)); +} + +void write_smp_table(void *v, unsigned long *processor_map) +{ + smp_write_floating_table(v); + smp_write_config_table(v, processor_map); +} + + diff --git a/src/mainboard/tyan/guiness/mptable.c b/src/mainboard/tyan/guiness/mptable.c index ee5a374a5b..089d46d971 100644 --- a/src/mainboard/tyan/guiness/mptable.c +++ b/src/mainboard/tyan/guiness/mptable.c @@ -3,7 +3,7 @@ #include #include -void smp_write_config_table(void *v) +void smp_write_config_table(void *v, unsigned long * processor_map) { static const char sig[4] = "PCMP"; static const char oem[8] = "TYAN "; @@ -28,7 +28,7 @@ void smp_write_config_table(void *v) mc->reserved = 0; - smp_write_processors(mc); + smp_write_processors(mc, processor_map); smp_write_bus(mc, 0, "PCI "); smp_write_bus(mc, 1, "PCI "); smp_write_bus(mc, 2, "ISA "); @@ -147,11 +147,11 @@ void smp_write_config_table(void *v) mc, smp_next_mpe_entry(mc)); } -void write_smp_table(void *v) +void write_smp_table(void *v, unsigned long *processor_map) { printk_debug("Writing the mp table\n"); smp_write_floating_table(v); - smp_write_config_table(v); + smp_write_config_table(v, processor_map); } diff --git a/src/northbridge/intel/440gx/Config b/src/northbridge/intel/440gx/Config index 2c738b0332..9c8c550f44 100644 --- a/src/northbridge/intel/440gx/Config +++ b/src/northbridge/intel/440gx/Config @@ -1,3 +1,4 @@ +mainboardinit arch/i386/lib/set_memory_size_noop.inc mainboardinit northbridge/intel/440gx/raminit.inc mainboardinit sdram/generic_sdram_enable.inc mainboardinit sdram/generic_sdram.inc diff --git a/src/northbridge/intel/440gx/reset_test.inc b/src/northbridge/intel/440gx/reset_test.inc index 7c743e5ec3..1aafb3eda6 100644 --- a/src/northbridge/intel/440gx/reset_test.inc +++ b/src/northbridge/intel/440gx/reset_test.inc @@ -1,23 +1,23 @@ - /* If I have already booted once skip a bunch of initialization */ + /* If I have already booted once skip a bunch of initialization */ #if 0 - /* To see if I have already booted I check to see if memory has - * been enabled. In this case by reading the memory size register. - * This gets set part way through the memory initialization but - * it should be fine for this purpose. - */ - movl $0x67, %eax - PCI_READ_CONFIG_BYTE - testb %al, %al - jnz __cpu_reset + /* To see if I have already booted I check to see if memory has + * been enabled. In this case by reading the memory size register. + * This gets set part way through the memory initialization but + * it should be fine for this purpose. + */ + movl $0x67, %eax + PCI_READ_CONFIG_BYTE + testb %al, %al + jnz __cpu_reset #endif #if 1 - /* To see if I have already booted I check to see if memory has - * been enabled. In this case by seeing if memory refresh - * hass ben enabled. - */ - movl $0x57, %eax - PCI_READ_CONFIG_BYTE - testb $0x7, %al - jnz __cpu_reset + /* To see if I have already booted I check to see if memory has + * been enabled. In this case by seeing if memory refresh + * hass ben enabled. + */ + movl $0x57, %eax + PCI_READ_CONFIG_BYTE + testb $0x7, %al + jnz __cpu_reset #endif diff --git a/src/northbridge/intel/82860/Config b/src/northbridge/intel/82860/Config new file mode 100644 index 0000000000..5191cb272f --- /dev/null +++ b/src/northbridge/intel/82860/Config @@ -0,0 +1 @@ +object northbridge.o diff --git a/src/northbridge/intel/82860/northbridge.c b/src/northbridge/intel/82860/northbridge.c new file mode 100644 index 0000000000..81e801b02c --- /dev/null +++ b/src/northbridge/intel/82860/northbridge.c @@ -0,0 +1,19 @@ +#include +#include +#include +#include + +unsigned long sizeram(void) +{ + unsigned long size; + unsigned short word; + + printk_notice("\nsizeram!!!\n"); + /* Read TOM */ + /* How should we handle > 4GB of ram? */ + pcibios_read_config_word(0, 0, 0xc4, &word); + /* Convert size in 64K bytes to size in K bytes */ + size = word << 6; + return size; + +} diff --git a/src/pc80/serial.inc b/src/pc80/serial.inc index 12057a06fb..96900359a5 100644 --- a/src/pc80/serial.inc +++ b/src/pc80/serial.inc @@ -1,24 +1,45 @@ - /* Base Address */ -#define TTYS0 0x3f8 +#ifndef TTYS0_BASE +#define TTYS0_BASE 0x3f8 +#endif + +/* Baud Rate */ +#ifndef TTYS0_BAUD +#define TTYS0_BAUD 115200 +#endif + +#if ((115200%TTYS0_BAUD) != 0) +#error Bad ttys0 baud rate +#endif + +/* Baud Rate Divisor */ +#define TTYS0_DIV (115200/TTYS0_BAUD) +#define TTYS0_DIV_LO (TTYS0_DIV&0xFF) +#define TTYS0_DIV_HI ((TTYS0_DIV >> 8)&0xFF) + +/* Line Control Settings */ +#ifndef TTYS0_LCS +/* Set 8bit, 1 stop bit, no parity */ +#define TTYS0_LCS 0x3 +#endif /* Data */ -#define TTYS0_RBR (TTYS0+0x00) +#define TTYS0_RBR (TTYS0_BASE+0x00) /* Control */ #define TTYS0_TBR TTYS0_RBR -#define TTYS0_IER (TTYS0+0x01) -#define TTYS0_IIR (TTYS0+0x02) +#define TTYS0_IER (TTYS0_BASE+0x01) +#define TTYS0_IIR (TTYS0_BASE+0x02) #define TTYS0_FCR TTYS0_IIR -#define TTYS0_LCR (TTYS0+0x03) -#define TTYS0_MCR (TTYS0+0x04) +#define TTYS0_LCR (TTYS0_BASE+0x03) +#define TTYS0_MCR (TTYS0_BASE+0x04) #define TTYS0_DLL TTYS0_RBR #define TTYS0_DLM TTYS0_IER /* Status */ -#define TTYS0_LSR (TTYS0+0x05) -#define TTYS0_MSR (TTYS0+0x06) -#define TTYS0_SCR (TTYS0+0x07) +#define TTYS0_LSR (TTYS0_BASE+0x05) +#define TTYS0_MSR (TTYS0_BASE+0x06) +#define TTYS0_SCR (TTYS0_BASE+0x07) jmp serial0 @@ -300,19 +321,21 @@ serial0: /* Set 115.2Kbps,8n1 */ /* Set 8bit, 1 stop bit, no parity, DLAB */ mov $TTYS0_LCR, %dx - mov $0x83, %al + mov $(TTYS0_LCS | 0x80), %al out %al, %dx /* set Baud Rate Divisor to 1 ==> 115200 Buad */ mov $TTYS0_DLL, %dx - mov $0x01, %al + mov $TTYS0_DIV_LO, %al out %al, %dx mov $TTYS0_DLM, %dx - mov $0x00, %al + mov $TTYS0_DIV_HI, %al out %al, %dx /* Disable DLAB */ mov $TTYS0_LCR, %dx - mov $0x03, %al + mov $(TTYS0_LCS & 0x7f), %al out %al, %dx + TTYS0_TX_STRING($ttyS0_test) + diff --git a/src/ram/ramtest.inc b/src/ram/ramtest.inc index bb823c1037..297c23a439 100644 --- a/src/ram/ramtest.inc +++ b/src/ram/ramtest.inc @@ -1,4 +1,3 @@ - /* * This is much more of a "Is my SDRAM properly configured?" * test than a "Is my SDRAM faulty?" test. Not all bits @@ -6,6 +5,7 @@ */ jmp rt_skip + .section ".rodata" rt_test: .string "Testing SDRAM : " rt_fill: .string "SDRAM fill:\r\n" @@ -13,6 +13,7 @@ rt_verify: .string "SDRAM verify:\r\n" rt_toomany: .string "Too many errors.\r\n" rt_done: .string "Done.\r\n" + .text ramtest: #ifdef RAMTEST mov %eax, %esi diff --git a/src/southbridge/intel/82801/82801.h b/src/southbridge/intel/82801/82801.h new file mode 100644 index 0000000000..5bf6c7ad13 --- /dev/null +++ b/src/southbridge/intel/82801/82801.h @@ -0,0 +1,2 @@ +#define SERIRQ_CNTL 0x64 +#define GEN_CNTL 0xd0 diff --git a/src/southbridge/intel/82801/Config b/src/southbridge/intel/82801/Config new file mode 100644 index 0000000000..57347e8e1b --- /dev/null +++ b/src/southbridge/intel/82801/Config @@ -0,0 +1,3 @@ +object nvram.o +object ich2_ioapic.o +object ich2_lpc.o diff --git a/src/southbridge/intel/82801/ich2_ioapic.c b/src/southbridge/intel/82801/ich2_ioapic.c new file mode 100644 index 0000000000..039abfe687 --- /dev/null +++ b/src/southbridge/intel/82801/ich2_ioapic.c @@ -0,0 +1,15 @@ +#include +#include +#include "82801.h" +void ich2_enable_ioapic(void) +{ + struct pci_dev *dev; + u32 dword; + dev = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_1F0, 0); + if (!dev) { + return; + } + pci_read_config_dword(dev, GEN_CNTL, &dword); + dword |= (3 << 7); + pci_write_config_dword(dev, GEN_CNTL, dword); +} diff --git a/src/southbridge/intel/82801/ich2_lpc.c b/src/southbridge/intel/82801/ich2_lpc.c new file mode 100644 index 0000000000..fd7ee80ff3 --- /dev/null +++ b/src/southbridge/intel/82801/ich2_lpc.c @@ -0,0 +1,13 @@ +#include +#include +#include "82801.h" +void ich2_enable_serial_irqs(void) +{ + struct pci_dev *dev; + u32 dword; + dev = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_1F0, 0); + if (!dev) { + return; + } + pci_write_config_byte(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0)); +} diff --git a/src/southbridge/intel/82801/nvram.c b/src/southbridge/intel/82801/nvram.c new file mode 100644 index 0000000000..891d8d20d6 --- /dev/null +++ b/src/southbridge/intel/82801/nvram.c @@ -0,0 +1,8 @@ +#include +#include + +void nvram_on(void) +{ + printk_notice("Please turn on nvram\n"); + return; +} diff --git a/src/southbridge/intel/82806/Config b/src/southbridge/intel/82806/Config new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/superio/winbond/w83627hf/setup_serial.inc b/src/superio/winbond/w83627hf/setup_serial.inc index 81375823e8..bcfb2b0c46 100644 --- a/src/superio/winbond/w83627hf/setup_serial.inc +++ b/src/superio/winbond/w83627hf/setup_serial.inc @@ -8,41 +8,50 @@ #define SIO_INDEX SIO_BASE #define SIO_DATA SIO_BASE+1 +#define SIO_SYSTEM_CLK_INPUT_48MHZ (1<<6) +#define SIO_SYSTEM_CLK_INPUT_24MHZ (0<<6) + +#if defined(SIO_SYSTEM_CLK_INPUT) +#if (SIO_SYSTEM_CLK_INPUT != SIO_SYSTEM_CLK_INPUT_48MHZ) && (SIO_SYSTEM_CLK_INPUT != SIO_SYSTEM_CLK_INPUT_24MHZ) +#error BAD SIO_SYSTEM_CLK_INPUT_PARAMETER +#endif +#endif + + #define SIO_COM1_DEVICE 2 #define SIO_ENTER_PNP_MODE() \ - movw $SIO_BASE, %dx ; \ - movb $0x87, %al ; \ - outb %al, %dx ; \ - outb %al, %dx + movb $0x87, %al ; \ + outb %al, $(SIO_BASE) ; \ + outb %al, $(SIO_BASE) #define SIO_EXIT_PNP_MODE() \ - movw $SIO_BASE, %dx ; \ - movb $0xaa, %al ; \ - outb %al, %dx + movb $0xaa, %al ; \ + outb %al, $(SIO_BASE) #define SIO_WRITE_CONFIG(value, reg) \ - movw $SIO_BASE, %dx ; \ - movb $reg, %al ; \ - outb %al, %dx ; \ - incw %dx ; \ - movb $value, %al ; \ - outb %al, %dx + movb $reg, %al ; \ + outb %al, $(SIO_INDEX) ; \ + movb $value, %al ; \ + outb %al, $(SIO_DATA) #define SIO_READ_CONFIG(value, reg) \ - movw $SIO_BASE, %dx ; \ - movb $reg, %al ; \ - outb %al, %dx ; \ - incw %dx ; \ - inb %al, %dx + movb $reg, %al ; \ + outb %al, $(SIO_INDEX) ; \ + inb %al, $(SIO_DATA) #define SIO_SET_LOGICAL_DEVICE(device) \ SIO_WRITE_CONFIG(device, 0x07) - - /* enable serial 1 */ + /* Enable pnp */ SIO_ENTER_PNP_MODE() + +#if defined(SIO_SYSTEM_CLK_INPUT) + /* Setup up the clock input */ + SIO_WRITE_CONFIG(0x84 | SIO_SYSTEM_CLK_INPUT), 0x24) +#endif + /* enable serial 1 */ SIO_SET_LOGICAL_DEVICE(SIO_COM1_DEVICE) SIO_WRITE_CONFIG(1, 0x30) SIO_WRITE_CONFIG(0x3, 0x60) diff --git a/src/superio/winbond/w83627hf/superio.c b/src/superio/winbond/w83627hf/superio.c index 790a8b6a08..9aff5d1363 100644 --- a/src/superio/winbond/w83627hf/superio.c +++ b/src/superio/winbond/w83627hf/superio.c @@ -249,8 +249,6 @@ static void enable_devices(struct superio *sio) setup_acpi_registers(sio); #endif - // what's this. - write_config(sio, 1, 0x30); exit_pnp(sio); } diff --git a/util/config/NLBConfig.py b/util/config/NLBConfig.py index fbe0aa15c0..a1f19111c2 100644 --- a/util/config/NLBConfig.py +++ b/util/config/NLBConfig.py @@ -42,7 +42,7 @@ def add_main_rule_dependency(new_dependency): # and an optional rule (can be empty) for actually building # the object def addobject(object, sourcepath, rule, condition): - objectrules.append([object, sourcepath, rule, condition]) + objectrules.append([object, topify(sourcepath), rule, condition]) # OK, let's face it, make sucks. # if you have a rule like this: @@ -98,12 +98,11 @@ def common_command_action(dir, type, name): return fullpath def set_arch(dir, my_arch): - global arch, makebase, crt0base, ldscriptbase + global arch, makebase, crt0base arch = my_arch configpath = os.path.join(treetop, os.path.join("src/arch/", os.path.join(my_arch, "config"))) makebase = os.path.join(configpath, "make.base") crt0base = os.path.join(configpath, "crt0.base") - ldscriptbase = os.path.join(configpath, "ldscript.base") print "Now Process the ", my_arch, " base files" if (debug): print "Makebase is :", makebase, ":" @@ -510,22 +509,6 @@ def writecrt0(path): file.close(); -# write ldoptions -def writeldoptions(path): - ldfilepath = os.path.join(path, "ldoptions") - print "Trying to create ", ldfilepath -# try: - file = open(ldfilepath, 'w+') - - keys = makeoptions.keys() - keys.sort() - for key in keys: - value = makeoptions[key] - regexp = re.compile(r"^(0x[0-9a-fA-F]+|0[0-7]+|[0-9]+)$") - if value and regexp.match(value): - file.write("%s = %s;\n" % (key, value)) - - file.close(); # write doxygen file def writedoxygenfile(path): @@ -554,38 +537,56 @@ def writedoxygenfile(path): +def topify(path): + global treetop + if path[0:len(treetop)] == treetop: + path = path[len(treetop):len(path)] + if (path[0:1] == "/"): + path = path[1:len(path)] + path = "$(TOP)/" + path + return path + + +def writemakefilesettings(path): + # Write Makefile.settings to seperate the settings + # from the actual makefile creation + # In practice you need to rerun NLBConfig.py to change + # these but in theory you shouldn't need to. + filename = os.path.join(path, "Makefile.settings") + + print "Trying to create ", filename + keys = makeoptions.keys() + keys.sort() +# try: + file = open(filename, 'w+') + file.write("TOP=%s\n" % (treetop)) + for key in keys: + file.write("export %s:=%s\n" % (key, makeoptions[key])) + file.write("export VARIABLES := "); + for key in keys: + file.write("%s " % key) + for key in makenooptions.keys(): + file.write("%s " % (key)) + file.write("\n"); + + # write the makefile # we're not sure whether to write crt0.S yet. We'll see. # let's try the Makefile # first, dump all the -D stuff def writemakefile(path): + writemakefilesettings(path) makefilepath = os.path.join(path, "Makefile") mainboardinitfiles = command_vals['mainboardinit'] config_file_list = command_vals['config_files'] ldscripts = command_vals['ldscripts'] print "Trying to create ", makefilepath - keys = makeoptions.keys() - keys.sort() -# try: file = open(makefilepath, 'w+') - file.write("TOP=%s\n" % (treetop)) - for key in keys: - if makeoptions[key] : - file.write("%s=%s\n" % (key, makeoptions[key])) - file.write("CPUFLAGS :=\n") - for key in keys: -# print "key is %s, val %s\n" % (key, makeoptions[key]) -# file.write("CPUFLAGS += %s\n" % (makeoptions[key])) - if makeoptions[key] : - file.write("CPUFLAGS += -D%s=\'%s'\n" % (key, makeoptions[key])) - else: - file.write("CPUFLAGS += -D%s\n" % (key)) - - for key in makenooptions.keys(): - file.write("CPUFLAGS += -U%s\n" % (key)) + file.write("include Makefile.settings\n") + file.write("include cpuflags\n") # print out all the object dependencies # There is ALWAYS a crt0.o @@ -599,9 +600,9 @@ def writemakefile(path): file.write("OBJECTS-$(%s) += %s\n" % (obj_cond, obj_name)) # print out all ldscript.ld dependencies - file.write("LDSUBSCRIPTS-1 := %s\n" % ldscriptbase ) + file.write("LDSUBSCRIPTS-1 := \n" ) for i in range(len(ldscripts)): - script = ldscripts[i][0]; + script = topify(ldscripts[i][0]); condition = ldscripts[i][1]; if condition: file.write("LDSUBSCRIPTS-$(%s) += %s\n" % (condition, script)) @@ -648,10 +649,10 @@ def writemakefile(path): # print out the dependencies for Makefile - file.write("Makefile crt0.S ldoptions nsuperio.c: %s $(TOP)/util/config/NLBConfig.py $(TOP)/src/arch/$(ARCH)/config/make.base $(TOP)/src/arch/$(ARCH)/config/crt0.base \n\tpython $(TOP)/util/config/NLBConfig.py %s $(TOP)\n" + file.write("Makefile Makefile.settings crt0.S nsuperio.c: %s $(TOP)/util/config/NLBConfig.py $(TOP)/src/arch/$(ARCH)/config/make.base $(TOP)/src/arch/$(ARCH)/config/crt0.base \n\tpython $(TOP)/util/config/NLBConfig.py %s $(TOP)\n" % (config_file, config_file)) for i in range(len(config_file_list)): - file.write("Makefile: %s\n" % config_file_list[i]) + file.write("Makefile: %s\n" % topify(config_file_list[i])) file.close(); # except IOError: @@ -685,7 +686,6 @@ treetop = command_vals['TOP'] # set the default locations for config files makebase = os.path.join(treetop, "util/config/make.base") crt0base = os.path.join(treetop, "arch/i386/config/crt0.base") -ldscriptbase = os.path.join(treetop, "arch/alpha/config/ldscript.base") doxyscriptbase = os.path.join(treetop, "src/config/doxyscript.base") ## now read in the base files. @@ -702,7 +702,6 @@ doconfigfile(treetop, config_file) # print key, val writemakefile(outputdir) -writeldoptions(outputdir) writecrt0(outputdir) writesuperiofile(outputdir) writedoxygenfile(outputdir)