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https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
suppoer for the acer aladdin chipset
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6 changed files with 168 additions and 0 deletions
1
src/mainboard/asus/cua/README
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src/mainboard/asus/cua/README
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This mainboard uses the Acer Aladdin TNT2 chipset.
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src/mainboard/asus/cua/ldscript.ld
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src/mainboard/asus/cua/ldscript.ld
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/*
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* Bootstrap code for the STPC Consumer
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* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
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*
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* $Id$
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*
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*/
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/* oh, barf. This won't work if all you use is .o's. -- RGM */
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/*
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* Written by Johan Rydberg, based on work by Daniel Kahlin.
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*/
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/*
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* We use ELF as output format. So that we can
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* debug the code in some form.
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*/
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OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
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OUTPUT_ARCH(i386)
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/*
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* Memory map:
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*
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* 0x00000 (4*4096 bytes) : stack
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* 0x04000 (4096 bytes) : private data
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* 0x05000 : data space
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* 0x90000 : kernel stack
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* 0xf0000 (64 Kbyte) : EPROM
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*/
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MEMORY
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{
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ram (rwx) : ORIGIN = 0x00000000, LENGTH = 128M /* 128 MB memory is
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* max for STPC */
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rom (rx) : ORIGIN = 0x000f0000, LENGTH = 128K /* 128 K EPROM */
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}
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_PDATABASE = 0x04000;
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_RAMBASE = 0x05000;
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_KERNSTK = 0x90000;
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/* should be parameterized but is not, yuck! */
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/*
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_ROMBASE = 0xe0000;
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*/
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_ROMBASE = 0xf0000;
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/*
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* Entry point is not really nececary, since the mkrom(8)
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* tool creates a entry point that jumps to $0xc000:0x0000.
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*/
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/* baloney, but ... RGM*/
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ENTRY(_start)
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SECTIONS {
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/*
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* First we place the code and read only data (typically const declared).
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* This get placed in rom.
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*/
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.text _ROMBASE : {
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_text = .;
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*(.text);
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*(.rodata);
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_etext = .;
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}
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_pdata = .;
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/*
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.pdata _PDATABASE : AT ( LOADADDR(.text) + SIZEOF(.text) +
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SIZEOF(.rodata)) {
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*/
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.pdata _PDATABASE : AT ( _etext ) {
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*(.pdata);
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}
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_epdata = LOADADDR(.pdata) + SIZEOF(.pdata);
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/*
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* After the code we place initialized data (typically initialized
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* global variables). This gets copied into ram by startup code.
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* __data_start and __data_end shows where in ram this should be placed,
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* whereas __data_loadstart and __data_loadend shows where in rom to
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* copy from.
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*/
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.data _RAMBASE : AT ( LOADADDR(.pdata) + SIZEOF(.pdata) ) {
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_data = .;
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*(.data)
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*(.sdata)
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*(.sdata2)
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*(.got)
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_edata = .;
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}
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_ldata = LOADADDR(.data);
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_eldata = LOADADDR(.data) + SIZEOF(.data);
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/*
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* bss does not contain data, it is just a space that should be zero
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* initialized on startup. (typically uninitialized global variables)
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* crt0.S fills between __bss_start and __bss_end with zeroes.
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*/
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.bss ( ADDR(.data) + SIZEOF(.data) ) : {
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_bss = .;
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*(.bss)
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*(.sbss)
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*(COMMON)
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_ebss = .;
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_heap = .;
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}
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}
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/*
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* This provides the start and end address for the whole image
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*/
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_image = LOADADDR(.text);
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_eimage = LOADADDR(.data) + SIZEOF(.data);
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/* EOF */
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19
src/mainboard/asus/cua/mainboard.c
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src/mainboard/asus/cua/mainboard.c
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#include <printk.h>
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#include <pci.h>
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#include <cpu/p5/io.h>
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void mainboard_fixup()
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{
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struct pci_dev *pm_pcidev, *host_bridge_pcidev, *nic_pcidev;
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unsigned smbus_io, pm_io;
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unsigned int i, j;
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printk("intel_mainboard_fixup()\n");
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#if 0
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// put in the right values for acer stuff
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pm_pcidev = pci_find_device(0x8086, 0x7113, 0);
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nic_pcidev = pci_find_device(0x8086, 0x1229, 0);
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host_bridge_pcidev = pci_find_slot(0, PCI_DEVFN(0,0));
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#endif
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}
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src/northbridge/acer/m1631/northbridge.c
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src/northbridge/acer/m1631/northbridge.c
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#include <pci.h>
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// FIX ME!
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unsigned long sizeram()
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{
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return 64*1024*1024;
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}
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#ifdef HAVE_FRAMEBUFFER
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void intel_framebuffer_on()
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{
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}
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#endif
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0
src/southbridge/acer/m1535/setup_serial.inc
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0
src/southbridge/acer/m1535/setup_serial.inc
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16
src/southbridge/acer/m1535/southbridge.c
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src/southbridge/acer/m1535/southbridge.c
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#include <pci.h>
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#include <pc80/keyboard.h>
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#include <printk.h>
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void
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southbridge_fixup()
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{
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}
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void nvram_on()
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{
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}
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void keyboard_on()
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{
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}
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