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https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
fixed a few bugs
This commit is contained in:
parent
70f4041200
commit
4703cc6ae6
2 changed files with 23 additions and 3 deletions
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@ -9,7 +9,10 @@ register_table:
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.byte 0x78, 0x1
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/* safe initial values ... */
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.byte 0x68, 0x0
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.byte 0x6a, 0x0 /* disable refresh */
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.byte 0x6b, 0x0
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.byte 0x6c, 0x0 /* disable ECC for start */
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.byte 0x6d, 0x37 /* as per Cindy Lee, ... */
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.byte 0x64, 0xe4 /* slowest ram setting. banks 0, 1 */
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.byte 0x65, 0xe4 /* banks 2, 3*/
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.byte 0x66, 0xe4 /* banks 4, 5 */
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@ -123,7 +126,7 @@ spd_set_nbxcfg_done:
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#define SET_RAM_COMMAND(command) \
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movl $0x6c, %eax ; \
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PCI_READ_CONFIG_BYTE ; \
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andl $0x14, %eax ; \
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andl $0x18, %eax ; \
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orl $(command), %eax ; \
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movl %eax, %edx ; \
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movl $0x6c, %eax ; \
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@ -135,7 +138,7 @@ spd_set_nbxcfg_done:
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PCI_READ_CONFIG_BYTE ; \
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andl $0x20, %eax ; \
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xorl $0x20, %eax ; \
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shll $2, %eax ; \
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shrl $1, %eax ; \
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orl $0x2a, %eax ; \
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#define SET_RAM_MODE_REGISTER \
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@ -154,6 +157,20 @@ spd_set_nbxcfg_done:
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#define ENABLE_REFRESH() CALL_LABEL(spd_enable_refresh)
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#endif
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#define FIRST_NORMAL_REFERENCE() \
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movl $0x55aa55aa, %eax; \
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mov %eax, 0x0; \
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mov 0x0, %eax;
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// should also read 0x5f and write that to 0x56 and 0x57
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#define SPECIAL_FINISHUP() \
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/* enable multi-page open */; \
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CS_WRITE($0x6B, $0x01)
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spd_enable_refresh:
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// just set it for now.
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CS_WRITE($0x6A, $0x65)
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@ -103,7 +103,8 @@ ram_initialize:
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/* normal operation */
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SET_RAM_COMMAND(RAM_COMMAND_NONE)
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FIRST_NORMAL_REFERENCE()
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TTYS0_TX_STRING($ram_8)
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@ -111,4 +112,6 @@ ram_initialize:
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/* DRAMC */
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ENABLE_REFRESH()
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SPECIAL_FINISHUP()
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TTYS0_TX_STRING($ram_9)
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