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UPSTREAM: soc/intel/quark: Pass S3 wake status to fsp_silicon_init

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Fix build error with FSP 1.1.  Pass the S3 wake status to
fsp_silicon_init.

TEST=Build and run on Galileo Gen2

Change-Id: Icd837562ee4ace32219296013f0fd818ba74ab07
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1e24bf3f71
Original-Change-Id: I78150f737321db5b1b4d63b411fa6432ac30d080
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18805
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/455824
This commit is contained in:
Lee Leahy 2017-03-13 17:13:39 -07:00 • committed by chrome-bot
parent 3670883d4b
commit 9f9f9e3f22
2 changed files with 3 additions and 3 deletions
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4
src/soc/intel/quark/fsp1_1.c
View file

@ -17,12 +17,12 @@
#include <fsp/util.h>
#include <soc/ramstage.h>
void fsp_silicon_init(void)
void fsp_silicon_init(bool s3wake)
{
if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM))
intel_silicon_init();
else
fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), 0);
fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), s3wake);
}
void soc_silicon_init_params(SILICON_INIT_UPD *upd)

2
src/soc/intel/quark/include/soc/ramstage.h
View file

@ -26,7 +26,7 @@
void mainboard_gpio_i2c_init(device_t dev);
#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
void fsp_silicon_init(void);
void fsp_silicon_init(bool s3wake);
#endif
asmlinkage void chipset_teardown_car(void);