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UPSTREAM: soc/intel/quark: Add ESRAM display to FSP 1.1

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Add ESRAM display to FSP 1.1

TEST=Build and run on Galileo Gen2

Change-Id: I945b0dbcb4c493863a196b5449494a4ceb38698d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 66b0d55d32
Original-Change-Id: Ia47b0bdba65606a7f0695332d298fc1e910b0e2f
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18804
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/455823
This commit is contained in:
Lee Leahy 2017-03-13 17:03:31 -07:00 • committed by chrome-bot
parent 9c1b53dca1
commit 3670883d4b
2 changed files with 33 additions and 1 deletions
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1
src/soc/intel/quark/Kconfig
View file

@ -177,7 +177,6 @@ config DCACHE_RAM_SIZE
config DISPLAY_ESRAM_LAYOUT
bool "Display ESRAM layout"
default n
depends on PLATFORM_USES_FSP2_0
help
Select this option to display coreboot's use of ESRAM.

33
src/soc/intel/quark/romstage/fsp1_1.c
View file

@ -105,6 +105,39 @@ void soc_memory_init_params(struct romstage_params *params,
if (!rmu_file)
die("Microcode file (rmu.bin) not found.");
/* Display the ESRAM layout */
if (IS_ENABLED(CONFIG_DISPLAY_ESRAM_LAYOUT)) {
printk(BIOS_SPEW, "\nESRAM Layout:\n\n");
printk(BIOS_SPEW,
"+-------------------+ 0x80080000 - ESRAM end\n");
if (_car_relocatable_data_end != (void *)0x80080000) {
printk(BIOS_SPEW, "| |\n");
printk(BIOS_SPEW, "+-------------------+ 0x%p\n",
_car_relocatable_data_end);
}
printk(BIOS_SPEW, "| coreboot data |\n");
printk(BIOS_SPEW, "+-------------------+ 0x%p\n",
_car_stack_end);
printk(BIOS_SPEW, "| coreboot stack |\n");
printk(BIOS_SPEW, "+-------------------+ 0x%p",
_car_stack_start);
if (IS_ENABLED(CONFIG_SEPARATE_VERSTAGE)) {
printk(BIOS_SPEW, "\n");
printk(BIOS_SPEW, "| vboot data |\n");
printk(BIOS_SPEW, "+-------------------+ 0x%08x",
CONFIG_DCACHE_RAM_BASE);
}
printk(BIOS_SPEW, " (CONFIG_DCACHE_RAM_BASE)\n");
printk(BIOS_SPEW, "| FSP data |\n");
printk(BIOS_SPEW, "+-------------------+\n");
printk(BIOS_SPEW, "| FSP stack |\n");
printk(BIOS_SPEW, "+-------------------+\n");
printk(BIOS_SPEW, "| FSP binary |\n");
printk(BIOS_SPEW,
"+-------------------+ 0x80000000 - ESRAM start\n\n");
}
/* Update the UPD data for MemoryInit */
upd->AddrMode = config->AddrMode;
upd->ChanMask = config->ChanMask;