Emulation/switch-coreboot
1
0
Fork 0
mirror of https://github.com/fail0verflow/switch-coreboot.git synced 2025-05-04 01:39:18 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

UPSTREAM: amd/bettong: Move OemPostParams() to correct file

Browse source 
The term 'callout' has a specific meaning in AGESA, meaning
invoking the said function from AGESA / PI proper.
OemPostParams() does not fall into that category.

BUG=none
BRANCH=none
TEST=none

Change-Id: If0c450bc95283f5d180750100ca2a2064af04912
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 353293580e
Original-Change-Id: I45913d93323b3813fc35b1dd1fdca3d782d4b01f
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19140
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/471463
This commit is contained in:
Kyösti Mälkki 2017-04-03 14:57:36 +03:00 • committed by chrome-bot
parent 38cea98d93
commit 95eef35a93
2 changed files with 21 additions and 23 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

23
src/mainboard/amd/bettong/BiosCallOuts.c
View file

@ -31,7 +31,6 @@
#include "BiosCallOuts.h" #include "BiosCallOuts.h"
#include "northbridge/amd/pi/dimmSpd.h" #include "northbridge/amd/pi/dimmSpd.h"
#include "northbridge/amd/pi/agesawrapper.h" #include "northbridge/amd/pi/agesawrapper.h"
#include <PlatformMemoryConfiguration.h>
#include <boardid.h> #include <boardid.h>
static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr);
@ -140,25 +139,3 @@ static AGESA_STATUS board_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr)
#endif #endif
return AGESA_SUCCESS; return AGESA_SUCCESS;
} }
#ifdef __PRE_RAM__
const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
MOTHER_BOARD_LAYERS (LAYERS_6),
MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
PSO_END
};
void OemPostParams(AMD_POST_PARAMS *PostParams)
{
if (board_id() == 'F') {
PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
}
}
#endif

21
src/mainboard/amd/bettong/OemCustomize.c
View file

@ -14,6 +14,8 @@
*/ */
#include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper.h>
#include <PlatformMemoryConfiguration.h>
#include <boardid.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
@ -132,3 +134,22 @@ VOID OemCustomizeInitEarly (
{ {
InitEarly->GnbConfig.PcieComplexList = &PcieComplex; InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
} }
static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
MOTHER_BOARD_LAYERS (LAYERS_6),
MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
PSO_END
};
void OemPostParams(AMD_POST_PARAMS *PostParams)
{
if (board_id() == 'F') {
PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
}
}