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UPSTREAM: google/eve: Fix DRAM DQS map

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This change fixes the two sets of pins that were swapped in the
map of DQS signals from CPU to DRAM for channel 1.

Although this does not appear to have any impact to the system it
does result in different register values for DQS pin mapping that
are programmed inside FSP.

BUG=chrome-os-partner:58666
TEST=This fix was verified against the current schematic and using
FSP debug output.

Change-Id: I71df31ad94bc1fb8f16b6677c00f0ac997b4303a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9471d00a4f
Original-Change-Id: I45b821071ba287493b3b13204b7f5b38e06eee75
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18279
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/438049
This commit is contained in:
Duncan Laurie 2017-02-01 16:37:29 -08:00 • committed by chrome-bot
parent 984a4db952
commit 92e5aaefa9
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/google/eve/romstage.c
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@ -32,7 +32,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
/* DQS CPU<>DRAM map */ /* DQS CPU<>DRAM map */
const u8 dqs_map[2][8] = { const u8 dqs_map[2][8] = {
{ 1, 0, 2, 3, 4, 5, 6, 7 }, { 1, 0, 2, 3, 4, 5, 6, 7 },
{ 1, 0, 4, 5, 3, 2, 7, 6 } }; { 1, 0, 5, 4, 2, 3, 7, 6 } };
/* Rcomp resistor */ /* Rcomp resistor */
const u16 rcomp_resistor[] = { 200, 81, 162 }; const u16 rcomp_resistor[] = { 200, 81, 162 };
/* Rcomp target */ /* Rcomp target */