From 92e5aaefa93acc95940cb7ac2d1a714970c8ccaa Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 1 Feb 2017 16:37:29 -0800 Subject: [PATCH] UPSTREAM: google/eve: Fix DRAM DQS map This change fixes the two sets of pins that were swapped in the map of DQS signals from CPU to DRAM for channel 1. Although this does not appear to have any impact to the system it does result in different register values for DQS pin mapping that are programmed inside FSP. BUG=chrome-os-partner:58666 TEST=This fix was verified against the current schematic and using FSP debug output. Change-Id: I71df31ad94bc1fb8f16b6677c00f0ac997b4303a Signed-off-by: Patrick Georgi Original-Commit-Id: 9471d00a4f5acc5697d52e18dd74f909560a9031 Original-Change-Id: I45b821071ba287493b3b13204b7f5b38e06eee75 Original-Signed-off-by: Duncan Laurie Original-Reviewed-on: https://review.coreboot.org/18279 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Aaron Durbin Original-Reviewed-by: Paul Menzel Reviewed-on: https://chromium-review.googlesource.com/438049 --- src/mainboard/google/eve/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/eve/romstage.c b/src/mainboard/google/eve/romstage.c index 4ae87fd4bb..2378e9052d 100644 --- a/src/mainboard/google/eve/romstage.c +++ b/src/mainboard/google/eve/romstage.c @@ -32,7 +32,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) /* DQS CPU<>DRAM map */ const u8 dqs_map[2][8] = { { 1, 0, 2, 3, 4, 5, 6, 7 }, - { 1, 0, 4, 5, 3, 2, 7, 6 } }; + { 1, 0, 5, 4, 2, 3, 7, 6 } }; /* Rcomp resistor */ const u16 rcomp_resistor[] = { 200, 81, 162 }; /* Rcomp target */