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Modify the artecgroup/dbe61 dts to be equivalent to v2 Config.lb. The

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target does not yet compile due to initram breakage, but the breakage is 
really old.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Marc Jones <marc.jones@amd.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@609 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Carl-Daniel Hailfinger 2008-02-18 17:20:47 +00:00
parent 26f198ee78
commit 79252b2ccc
1 changed files with 19 additions and 1 deletions
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20
mainboard/artecgroup/dbe61/dts
View file

@ -84,8 +84,26 @@ end
pci@1,0 {
/config/("northbridge/amd/geodelx/pci");
};
pci@1,1 {
pci@15,0 {
/config/("southbridge/amd/cs5536/dts");
/* Interrupt enables for LPC bus.
* Each bit is an IRQ 0-15. */
lpc_serirq_enable = "0x00001002";
/* LPC IRQ polarity. Each bit is an IRQ 0-15. */
lpc_serirq_polarity = "0x0000effd";
/* 0:continuous 1:quiet */
lpc_serirq_mode = "1";
/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none.
* See virtual PIC spec. */
enable_gpio_int_route = "0x0D0C0700";
/* COM1 settings */
com1_enable = "0";
com1_address = "0x2f8";
com1_irq = "3";
/* COM2 settings */
com2_enable = "1";
com2_address = "0x3f8";
com2_irq = "4";
};
};
};